Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-02-28
2004-04-20
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S238500
Reexamination Certificate
active
06724663
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to non-volatile memories and in particular the present invention relates to erase architectures for a non-volatile flash memory.
BACKGROUND OF THE INVENTION
Memory devices are available in a variety of styles and sizes. Some memory devices are volatile in nature and cannot retain data without an active power supply. A typical volatile memory is a DRAM which includes memory cells formed as capacitors. A charge, or lack of charge, on the capacitors indicate a binary state of data stored in the memory cell. Dynamic memory devices require more effort to retain data than non-volatile memories, but are typically faster to read and write.
Non-volatile memory devices are also available in different configurations. For example, floating gate memory devices are non-volatile memories that use floating gate transistors to store data. The data is written to the memory cells by changing a threshold voltage of the transistor and is retained when the power is removed. To erase these transistors, a time consuming operation is performed to accurately restore the threshold voltage of the transistor. Because of this time consuming process, the memory may be arranged in erase blocks where all of the memory cells in an erase block are erased at one time. These non-volatile memory devices are commonly referred to a flash memories. While all operations of the flash memory devices are not as fast as volatile memory, advances have been experienced that make them practical replacements for some dynamic memories in processing systems.
Implementing flash memory devices can require a change in system designs to accommodate the unique aspects of the memory device. For example, programming data can require more time than storing data to a DRAM. Further, maintaining related data within a single erase block is important. That is, splitting data between two different erase blocks could result in the loss of some data due to erasure.
DRAM and flash memory devices typically have different architectures as dictated by their operation or the demands of the operating environment. As flash memory becomes a viable alternative to DRAM, a common architecture will become increasing important. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory that can be implemented in a processing system while maintaining a similar configuration as a volatile memory.
SUMMARY OF THE INVENTION
The above-mentioned problems with non-volatile memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification. The present invention provides a non-volatile memory that has a scrambled addressing pattern to align erase blocks primarily with array rows and secondarily with array columns.
In one embodiment, a non-volatile memory device comprises an array of memory cells arranged in rows and columns, and sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns. Each group of sense amplifiers defines a page of the memory array. Addressing circuitry is provided to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
In another embodiment, a non-volatile memory comprises an array of memory cells arranged in rows and columns, and sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns. Each group of sense amplifiers defines a page of the memory array. Erase circuitry is provided to erase blocks of the array, wherein the blocks are aligned with the memory array rows such that they cross the plurality of pages.
A flash memory device comprises an array of floating gate memory cells arranged in rows and columns, and sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns. Each group of sense amplifiers defines a page of the memory array. Erase circuitry is provided to erase blocks of the array, wherein the blocks are aligned with the memory array rows such that they cross the plurality of pages. Addressing circuitry is provided to access the array, wherein addresses of the memory cells are scrambled such that each erase block contains linear addresses.
A method of operating a non-volatile memory device comprises storing data in a plurality of adjacent array pages sharing common row addresses, and erasing a block of memory cells, wherein the block comprises columns of memory cells located in the plurality of pages.
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Roohparvar Frankie Fariborz
Widmer Kevin C.
Leffert Jay & Polglaze P.A.
Nguyen Tan T.
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