Erase and program verification circuit for non-volatile memory

Details Erase and program verification circuit for non-volatile memory Erase and program verification circuit for non-volatile memory

1995-05-19

1996-06-18

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular biasing

36518522, 36518909, 36518516, 36518513, 3651853, G11C 700

Patent

active

055285465

ABSTRACT:
For non-volatile memory devices, such as flash EPROM integrated circuits, which have memory cells and reference cells, and sense circuitry responsive to addressed memory cells and the reference cells, and in which a read potential is supplied to the gate of the selected memory cells and a reference potential is supplied to the gate of a reference memory cell during a read mode, the state of the programmable memory cells is verified by (1) supplying a first verify potential to the gate of an address programmable memory cell; and (2) supplying a second verify potential to the gate of the reference cell which is different from the first verify potential. Because cell current is a very strong function of the gate voltage, applying different gate voltages to the memory and reference cells is equivalent to adjusting the sense ratio. When the method is applied for program verify, then the second verify potential applied to the reference cell is less than the first verify potential applied to the addressed programmable memory cell. When the method is applied for erase verify, the second verify potential is greater than the first verify potential.

REFERENCES:
patent: 5091888 (1992-02-01), Akaog
patent: 5117394 (1992-05-01), Amin et al.
patent: 5142496 (1992-08-01), Van Buskirk
patent: 5163021 (1992-11-01), Mehrotra et al.

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