Erase algorithm for multi-level bit flash memory

Details Erase algorithm for multi-level bit flash memory Erase algorithm for multi-level bit flash memory

2007-07-31

2007-07-31

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185290, C365S185300

Reexamination Certificate

active

10864947

ABSTRACT:
Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells. Optionally, the algorithm may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user.

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International Search Report, Int'l Application No. PCT/US2005/004539, Int'l Filing Date Feb. 11, 2005, 2 pgs.

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