Erasable read-only semiconductor memory device

Details Erasable read-only semiconductor memory device Erasable read-only semiconductor memory device

1988-10-06

1990-08-14

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365184, 357 235, G11C 700

Patent

active

049493051

ABSTRACT:
Memory transistors are arranged in a plurality of rows and a plurality of columns. A source line is formed for every two bit lines formed in the column direction, each connected to the memory transistors of one column. A source region of each memory transistor is connected, on one side, to a source line adjacent thereto and, on the other side, to a source line through the source region of the adjacent memory transistor, through impurity regions respectively. A floating gate is formed to extend to a position under the corresponding source line. In another example, a source line is formed for each bit line formed in the column direction. The source region of each memory transistor is connected to the adjacent source lines on both sides thereof through impurity regions. The floating gate is formed to extend to positions under both adjacent source lines.

REFERENCES:
patent: 4425632 (1984-01-01), Iwahashi et al.
patent: 4453234 (1984-06-01), Uchida
Saigo et al., "A 20K-Gate CMOS Gate Array", IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, (Oct. 1983), pp. 578-584.
M. Van Buskirk et al., "E-PROMS Graduate to 256-K Density with Scaled n-Channel Process", Electronics, Feb. 24, 1983, pp. 4-112-4-117.

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