Erasable programmable read only memory device improved in operat

Details Erasable programmable read only memory device improved in operat Erasable programmable read only memory device improved in operat

1989-12-27

1991-01-01

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

357 235, 357 2312, G11C 1140

Patent

active

049823779

ABSTRACT:
An erasable programmable read only memory device includes a plurality of memory cells arranged in rows and columns, a plurality of word lines associated with the rows of the memory cells, respectively, and a plurality of digit line pairs respectively associated with the columns of the memory cells, each of the digit line pairs consists of a first digit line for a reading out operation and a second digit line for a write in operation, and each memory cell comprises a series combination of a selecting transistor of an enhancement type and a reading out transistor of a depletion type coupled between the first digit line and a source of constant voltage level and a write-in transistor of the enhancement type coupled between the second digit line and the source of constant voltage level and higher in impurity concentration than the read-out transistor for production of a large amount of hot carriers, in which a floating gate is shared between the reading out transistor and the write-in transistor for injecting the hot carriers from the write-in transistor into the floating gate at a high efficiency, and in which a control gate is coupled to one of the word lines and shared between the selecting transistor, the reading out transistor and the write-in transistor, so that the selecting transistor suppresses leakage current from the first digit line.

REFERENCES:
patent: 4580247 (1986-04-01), Adam
patent: 4622656 (1986-11-01), Kamiya et al.
patent: 4683554 (1987-07-01), Lockwood et al.
patent: 4821236 (1989-04-01), Hayashi et al.
patent: 4868629 (1989-09-01), Eitan
patent: 4907198 (1990-03-01), Arima

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