Erasable programmable memory

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36518901, 36523001, 357 235, G11C 1300

Patent

active

049966685

ABSTRACT:
EEPROM memories with crosspoint cells using buried source and drain lines plus merged floating gate transistors with floating gate coupling to control gate over the buried line insulator for high packing plus low voltage operation.

REFERENCES:
patent: 4405995 (1983-09-01), Shirai et al.
patent: 4561004 (1985-12-01), Kuo et al.
patent: 4590504 (1986-05-01), Guterman
patent: 4750024 (1988-06-01), Schreck
patent: 4912676 (1990-03-01), Paterson et al.

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