Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-12-13
2001-04-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185200, C365S185290
Reexamination Certificate
active
06222764
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor memories, and, more particularly, to an electrically erasable programmable read only memory (EEPROM).
BACKGROUND OF THE INVENTION
Non-volatile memories are used in a variety of products because they retain their contents even when power is no longer supplied. An electrically erasable programmable read only memory (EEPROM) is a type of non-volatile memory that permits the contents to be erased and different data to be stored therein.
A typical EEPROM device includes an array of memory cells, and, each memory cell includes a floating gate and a control gate over the floating gate. The floating gate is positioned over a channel of the transistor that is defined between spaced apart source and drain regions formed in a semiconductor substrate. Intervening insulating layers are between the channel and floating gate, and between the floating gate and control gate. One type of memory cell configuration is a stacked gate arrangement wherein the control gate is directly over the floating gate. Another type of memory cell configuration is the split gate arrangement wherein the control gate extends over the floating gate, but also extends laterally adjacent the floating gate over a portion of the channel of the transistor.
A disadvantage of the stacked and split gate arrangements is that they can not be manufactured through the standard complementary metal oxide semiconductor (CMOS) process. This is due to the standard CMOS process using a single layer polysilicon deposition step whereas the stacked and split gate arrangements require two polysilicon deposition steps for the floating gate and the control gate.
A CMOS EEPROM with the control gate and the floating gate formed with a single poly layer is disclosed in U.S. Pat. No. 5,886,376 to Ohsaki and in an article titled “A Single Poly EEPROM Cell Structure For Use In Standard CMOS Process”, by Ohsaki et al., IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, March 1994. The disclosed single poly layer memory cell includes adjacently placed NMOS and PMOS transistors. A common polysilicon gate with respect to the NMOS and PMOS transistors serves as the floating gate, and the well region of the PMOS transistor serves as the control gate for the memory cell.
However, there are two problems with erasing a single poly layer memory cell as disclosed in the Ohsaki patent and in the Ohsaki et al. article. One approach to erasing a charge of the floating gate requires a high erase voltage applied to the spaced apart source and drain regions and to the n-well of the PMOS transistor while the NMOS transistor is grounded. When the gate capacitance ratio, i.e., a ratio of the capacitance of the gate of the PMOS transistor to the capacitance of the gate of the NMOS transistor, is much greater than 1, the high erase voltage approaches the junction breakdown voltage of the n-well to the p-well which is about 13 to 15 volts for 0.25 micron technology. A well or tub breakdown reduces device reliability and data retention.
Another approach to erasing a charge of the floating gate requires a high erase voltage applied to the spaced apart source and drain regions of the NMOS transistor while the PMOS transistor is grounded. Depending on the gate capacitance ratio, this high erase voltage approaches the junction breakdown of the PMOS transistor, which is about 7 to 9 volts for 0.25 micron technology. A drain voltage close to the junction breakdown voltage during erase can lead to hole injection into the floating gate, and can thus reduce device reliability and data retention.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an erasable memory device and an associated method for erasing a memory cell therein without reducing device reliability and data retention of the erased memory cell.
This and other objects, advantages and features in accordance with the present invention are provided by an electrically erasable memory device comprising a substrate and a plurality of memory cells in the substrate. Each memory cell preferably comprises a first region having a first conductivity type in the substrate, and a first MOS transistor in the first region and comprising spaced apart source and drain regions defining a channel therebetween and a gate overlying the channel. A second region having a second conductivity type in the substrate is preferably laterally adjacent to the first region wherein a capacitor comprising a first electrode preferably overlies the second region and an insulating layer is therebetween, and a third region having the first conductivity type is preferably in the second region defining a second electrode. The gate of the first MOS transistor and the first electrode of the capacitor are preferably connected together to define a floating gate, and the second region of the capacitor preferably serves as a control gate. In other words, the floating gate and the control gate of the memory cell are formed as a result of a single poly layer deposition step during the CMOS process.
The electrically erasable memory device preferably further comprises an erasing circuit for selectively erasing at least one of the memory cells by supplying a first voltage reference of a first polarity to the spaced apart source and drain regions of the first MOS transistor, a second voltage reference of a second polarity to the first region, and a third voltage reference of the second polarity to the second electrode in the third region.
The first and second voltage references advantageously bias the first MOS transistor so that the third voltage reference for erasing the selected memory cell does not cause a junction breakdown of the first MOS transistor. In other words, the bias voltage applied to the first MOS transistor allows a lower erase voltage to be applied to the memory cell for removing a charge of the floating gate. In addition, when the bias voltage is applied to the first MOS transistor, the time required for erasing the data is significantly reduced. This aspect of the invention is particularly advantageous when the gate capacitance ratio, i.e., a ratio of the capacitance of the capacitor to the capacitance of the gate of the first MOS transistor, is greater than 1.
The first voltage reference preferably has an absolute value less than about 7 volts, the second voltage reference preferably has an absolute value in a range of about 0 to 2 volts, and the third voltage reference has an absolute value in a range of about 3 o 7 volts. Depending on the technology size of the electrically erasable memory device, the third voltage reference is such that it does not cause a junction breakdown of the first MOS transistor as a result of the first and second voltage references. The first conductivity type is preferably P conductivity type, and the second conductivity type is preferably N conductivity type.
Another aspect of the present invention relates to a method for erasing a single poly layer memory cell in an electrically erasable memory device. The method preferably comprises the steps of supplying a first voltage reference of a first polarity to spaced apart source and drain regions of a first MOS transistor in a first region of a first conductivity type of the single poly layer memory cell; supplying a second voltage reference of a second polarity to the first region; and supplying a third voltage reference of the second polarity to an electrode of a capacitor in a second region laterally adjacent the first region.
The first and second voltage references preferably bias the first MOS transistor so that the third voltage reference for erasing the single poly memory cell does not cause a junction breakdown of the first MOS transistor.
REFERENCES:
patent: 5465231 (1995-11-01), Ohsaki
patent: 5604700 (1997-02-01), Parris et al.
patent: 5942936 (1999-08-01), Ricco et al.
patent: 6064595 (2000-05-01), Logie et al.
“A Single Poly EEPROM Cell Structure for Use in Standard CMOSProcess”, Ohsaki et al., IEEE Journal of Solid State Circuits, vol. 29, No. 3
Kelley Patrick J.
Leung Chung Wai
Singh Ranbir
Agere Systems Guardian Corp.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Le Thong
Nelms David
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