Erasable frohmann-bentchkowsky memory transistor that stores mul

Details Erasable frohmann-bentchkowsky memory transistor that stores mul Erasable frohmann-bentchkowsky memory transistor that stores mul

1999-09-10

2000-12-05

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518528, 36518529, G11C 1604

Patent

active

061575747

ABSTRACT:
Multiple bits of data are stored in an erasable Frohmann-Bentchkowsky p-channel memory transistor which has a plurality of upper plates that are switchably connectable to an erase voltage. The multiple bits of data define a number of logic states which, in turn, define a number of corresponding charge ranges on the floating gate. The charge ranges include a first charge range and a plurality of remaining charge ranges. Each remaining charge range is associated with a different combination of upper plates. Electrons are injected onto the floating gate so that the charge on the floating gate falls within the first charge range. To place the charge within one of the remaining charge ranges, electrons are removed from the floating gate by connecting the upper plates that are associated with the desired charge range to the erase voltage to partially erase the transistor.

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