Erasable and programmable single chip clock generator

Details Erasable and programmable single chip clock generator Erasable and programmable single chip clock generator

1995-10-30

1997-11-04

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 2, 331108C, 331 74, 327147, 455260, H03L 716, H03L 707

Patent

active

056844344

ABSTRACT:
A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

REFERENCES:
patent: 4882549 (1989-11-01), Galani et al.
patent: 4980653 (1990-12-01), Shepherd
patent: 5142247 (1992-08-01), Lada, Jr. et al.
patent: 5144254 (1992-09-01), Wilke
patent: 5289138 (1994-02-01), Wang

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