Erasable and programmable read-only memory system

Details Erasable and programmable read-only memory system Erasable and programmable read-only memory system

1988-07-28

1990-10-30

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518911, 307463, G11C 800

Patent

active

049673998

ABSTRACT:
Am EPROM system comprising a memory cell array formed of a matrix of non-volatile semiconductor memory cells, each having a control gate and a floating gate, and storing electric charges on the floating gate, and a word line drive circuit driving respective word lines connected to the control gates of the respective memory cells. The word line drive circuit comprises a delay circuit for delaying a first selection signal, a boosting capacitor having a first electrode connected to the first selection signal and a second electrode connected the output of the delay circuit, and MOS transistors each having a gate electrode connected the second electrode of the boosting capacitor, a first electrode connected to receive a second selection signal and a second electrode connected to a word line.

REFERENCES:
patent: 4455629 (1984-06-01), Suzuki et al.
patent: 4622479 (1986-11-01), Taylor
patent: 4704706 (1987-11-01), Nakano et al.
patent: 4806798 (1989-02-01), Kanauchi
patent: 4814647 (1989-03-01), Tran
"Nonvolatile Memories" 1984 IEEE International Solid-State Circuits Conference, Feb. 23rd, 1984, pp. 136-137.

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