Equalized capacitance wiring method for LSI circuits

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357 41, 357 45, 364491, H01L 2702, H01L 2710, H03H 2100, H04B 300

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046944036

ABSTRACT:
A method for equalizing the capacitances of a plurality of circuits in order to compensate for different signal transmission delay times within an LSI circuit. The wiring capacitance of the individual circuits are measured and the maximum capacitance value in a circuit group is determined. An equalizing capacitance pattern, which has a capacitance corresponding to the difference between the maximum capacitance value and the capacitance value of an individual circuit, is applied to each individual circuit.

REFERENCES:
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Trimberger, Stephen, "Automating Chip Layout", IEEE Spectrum, Jun. 1981, vol. 19, No. 6, pp. 38-45.
Daniel et al., "CAD Systems for IC Design", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. CAD-1, No. 1, Jan. 1982, pp. 2-12.
"IEEE Transactions on Mircrowave Theory and Techniques", Dec. 1966, vol. MTT-14, pp. 696.varies.698.
IBM Journal of Research and Development, vol. 25, No. 3, May, 1981 "Bipolar Circuit Design for a 5000-Circuit VLSI Gate Array" A. H. Dansky.
"Philo--A VLSI Design System", pp. 163-169, M. Jenkins et al 19th Design Automation Conference, 1982.

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