Equalized biased array for PROMS and EPROMS

Details Equalized biased array for PROMS and EPROMS Equalized biased array for PROMS and EPROMS

1985-10-15

1988-01-26

Popek, Joseph A.

Static information storage and retrieval

Powering

365104, G11C 700

Patent

active

047220759

ABSTRACT:
An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V.sub.BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V.sub.T above V.sub.BIAS. Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V.sub.T about V.sub.BIAS. The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.

REFERENCES:
patent: 4301518 (1981-11-01), Klaas
patent: 4314362 (1982-02-01), Klaas et al.
patent: 4344154 (1982-08-01), Klaas et al.
patent: 4387447 (1983-06-01), Klaas et al.

Affiliated with

Also associated with

Rating

Equalized biased array for PROMS and EPROMS does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Equalized biased array for PROMS and EPROMS, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Equalized biased array for PROMS and EPROMS will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1471967