Equalization pulse generating circuit for memory device

Details Equalization pulse generating circuit for memory device Equalization pulse generating circuit for memory device

1996-08-23

1999-05-25

Zarabian, A.

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 800

Patent

active

059075201

ABSTRACT:
A circuit for generating equalization pulses for a memory device is disclosed, which prevents formation of a short circuit between a Vdd potential and a Vss potential when two address transition signals are successively generated, and which generates the equalization pulses by using address transition pulses and by reducing the access time of the memory device. The equalization pulse generating circuit includes a NAND circuit section for outputting a NAND logic of address transition signals under address transitions to an equalization pulse generating node, a delay circuit section for delaying an output of the equalization pulse generating node for a certain period of time, so as to generate at least one delayed output signal, and a maintaining circuit section for logically processing the delayed output signal of the delay circuit section and the NAND logic output of the NAND circuit section, so as to maintain the state of the equalization pulse generating node in the same state for a certain period of time.

REFERENCES:
patent: 4614883 (1986-09-01), Sood et al.
patent: 4636991 (1987-01-01), Flannagan et al.
patent: 5418479 (1995-05-01), Sambandan
patent: 5627796 (1997-05-01), Park
patent: 5633833 (1997-05-01), Yoon

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