EPROM with increased floating gate/control gate coupling

Details EPROM with increased floating gate/control gate coupling EPROM with increased floating gate/control gate coupling

1987-09-11

1989-08-08

James, Andrew J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 236, 357 2311, 357 47, 357 49, 357 55, 365185, H01L 2978, H01L 2952, H01L 2906

Patent

active

048558001

ABSTRACT:
Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

REFERENCES:
patent: 4377818 (1983-03-01), Kuo et al.
patent: 4477310 (1984-10-01), Park et al.
patent: 4561004 (1985-12-01), Kio et al.
patent: 4597060 (1986-06-01), Mitchell et al.
patent: 4612629 (1986-09-01), Harari
patent: 4686558 (1987-08-01), Adam
patent: 4698900 (1987-10-01), Esquirel
patent: 4729006 (1988-03-01), Dally et al.
patent: 4750024 (1988-06-01), Schreck

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