EPROM with increased floating gate/control gate coupling

Details EPROM with increased floating gate/control gate coupling EPROM with increased floating gate/control gate coupling

1989-04-11

1990-01-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 48, 437 67, 437233, 437193, 156653, 357 235, H01L 21269

Patent

active

048928402

ABSTRACT:
Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

REFERENCES:
patent: 4426764 (1984-01-01), Kosa
patent: 4517732 (1985-05-01), Ashikawa
patent: 4519849 (1985-05-01), Karsh et al.
patent: 4561004 (1985-12-01), Kuo
patent: 4597060 (1986-06-01), Mitchell
patent: 4616402 (1986-10-01), Mori
patent: 4698900 (1987-10-01), Esquivel
patent: 4729006 (1988-03-01), Dally

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