Eprom memory matrix with symmetrical elementary MOS cells and wr

Details Eprom memory matrix with symmetrical elementary MOS cells and wr Eprom memory matrix with symmetrical elementary MOS cells and wr

1985-10-03

1988-12-20

Moffitt, James W.

Static information storage and retrieval

Floating gate

Particular biasing

G11C 1140

Patent

active

047929251

ABSTRACT:
The invention provides an EPROM memory matrix and a method of writing to an EPROM memory matrix. Two pluralities of parallel source lines alternate with parallel drain lines while floating gate areas span the source and drain lines and parallel control gate lines are arranged perpendicularly to the source and drain lines and superimposed on and self-aligned with the floating gate areas. During the writing operation, the gate and drain lines corresponding to a selected cell are connected to a positive voltage source and the source line corresponding to the selected cell is connected to earth together with all the other source lines of the same plurality while all the source lines of the other plurality are left at a potential intermediate between said positive voltage and earth.

REFERENCES:
patent: 4282446 (1981-08-01), McElroy
patent: 4451904 (1984-05-01), Sugiura et al.
patent: 4472792 (1984-09-01), Shimohigashi et al.
patent: 4594689 (1986-06-01), Donoghue

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