EPROM latch circuit

Details EPROM latch circuit EPROM latch circuit

1987-01-22

1989-02-07

Hecker, Stuart N.

Static information storage and retrieval

Read only systems

365189, 365185, 365104, 307554, G11C 700, G11C 1700, G11C 1134, G11C 1140

Patent

active

048036595

ABSTRACT:
A latch circuit provides for a reading of a state of an EPROM cell and retains that state after the reading sequence is completed. The memory state of the EPROM is inputted to a NOR gate during a power on reset condition. The output of the NOR gate is fed back through an inverter to the input of the NOR gate, such that when the EPROM is deactivated, the input of the NOR gate is latched to the previous EPROM memory state.

REFERENCES:
patent: 4275316 (1981-06-01), Knapp
patent: 4651303 (1987-03-01), Dias et al.
patent: 4686652 (1987-08-01), Spence

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