EPROM IC having reduced impurity regions

Details EPROM IC having reduced impurity regions EPROM IC having reduced impurity regions

1989-10-04

1990-06-19

Carroll, J.

357 233, 357 234, 357 235, 357 238, 357 41, H01L 2978, H01L 2702, H01L 2934

Patent

active

049358022

ABSTRACT:
A semiconductor integrated circuit which is of entire microstructure so as to reduce a gate length as to an EPROM formed on a substrate, thereby increasing the quantity of a current flowing between a source and a drain and, on the other hand, a transistor portion other than the EPROM on the same substrate is of structure for weakening the electric field between the source region and the drain region by means of the LDD technique or the like, thereby preventing the occurrence of a breakdown in the channel caused by hot electrons.

REFERENCES:
patent: 4536944 (1985-08-01), Bracco et al.
patent: 4622737 (1986-04-01), Ravaglia
patent: 4656492 (1987-09-01), Sunami et al.
patent: 4811075 (1989-03-01), Eklund
M. Woods, "Motion Analysis of EPROM and Various Ways of Inspection" Nikkei Electronics (Jan. 1981) pp. 181-201.
J. Sasaki, "Fine CMOS Process which Compares 256K SRAM", Electron Materials (Jun. 1985) pp. 35-39.

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