EPROM having a reduced number of contacts

Static information storage and retrieval – Magnetic bubbles – Guide structure

Patent

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Details

365185, 365184, 365104, H01L 2701, H01L 2900, H01L 2978

Patent

active

050179780

ABSTRACT:
An integrated circuit includes a memory having cells arranged in rows and columns, each cell having transistor being connected between two bit lines and having a current channel, a control gate and a charge-storage region therebetween, neighboring cells in a same row having a bit line contact in common, and control gates of transistors in a row being connected to a same word line, wherein each transistor has in a substrate of a first conductivity type a source region, a drain region and an injector region of a second conductivity type and mutually separated from each other, the injector regions of the transistors in a first row being controllable via the bit line contacts of the transistors in a second row adjacent to said first row. Preferably, at least one source region, at least one drain region and at least one injector region that are connected to a same bit line contact form a coherent region, e.g. a well, in the substrate. Preferably, the first and second row have the word line in common. The multiple use of bit line and word lines contribute to a dense memory.

REFERENCES:
patent: 4112509 (1978-09-01), Wall
patent: 4184207 (1980-01-01), McElroy
patent: 4281397 (1981-07-01), Neal et al.
patent: 4334292 (1982-06-01), Kotecha
patent: 4887238 (1989-12-01), Bergemont
patent: 4905194 (1990-02-01), Ohtsuka et al.
patent: 4912676 (1990-03-01), Paterson et al.
patent: 4930105 (1990-05-01), Matsumoto et al.

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