EPROM/flash EEPROM cell and array configuration

Static information storage and retrieval – Floating gate – Particular biasing

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365104, G11C 1140

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active

048887340

ABSTRACT:
An EPROM structure incorporating Vss isolation transistors having gates on wordlines shared by respective rows of conventional self-aligned EPROM cells, and having source and drain regions connected in series between EPROM cell source regions and the ground Vss terminal. An isolation transistor becomes conductive only when an EPROM cell sharing its wordline is selected. During programming, otherwise possible leakage current through unselected cells sharing the selected bitline is blocked by the Vss isolation transistor. Only one unselected adjacent cell, which shares a common source region with the selected cell, can leak. This leakage, if properly suppressed and compensated, has no disturbance on unselected or selected cells during array programming. The EPROM cell drain punchthrough voltage and channel length can thus be reduced to obtain an EPROM cell with a low threshold voltage, low drain programming voltage, short programming time, low cell junction and bitline capacitance, and high read current. EPROM-type products can be constructed with single low power supplies, on-chip high voltage pumping and high speed read and programming. Additional rows of shared isolation transistors can be formed by adding extra poly2 lines in parallel to the wordlines between EPROM source diffusions to achieve fuller programming isolation. This cell and array isolation configuration can be extended to flash EEPROM type products.

REFERENCES:
patent: 4328565 (1982-05-01), Harari
patent: 4467453 (1984-08-01), Chiu et al.
patent: 4639893 (1987-01-01), Eitan
patent: 4783766 (1988-11-01), Samachisa et al.
G. Samachisa, "A 128K Flash EEPROM Using . . . ", IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct. 1987.

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