EPROM fabrication process

Details EPROM fabrication process EPROM fabrication process

1988-01-11

1989-05-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437043, 437045, 437052, 437195, 437240, 437228, 357 235, H01L 2996

Patent

active

048309745

ABSTRACT:
An EPROM fabrication process using CMOS N-well technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a large process tolerance latitudes, a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high temperature drive-in and oxidation cycle with a 1000-2500 .ANG. thick nitride mask covering device areas. The floating gate stack is formed by forming a first gate oxide layer depositing a first polysilicon layer having a thickness of 2000-2600 .ANG., removing these layers from non-memory cell areas, growing a uniformly thick second oxide layer at 1100.degree.-1200.degree. C. over both the substrate and first polysilicon layer, depositing a second polysilicon gate layer and selectively etching away the layers to form first the device gates and second memory all gate from the second polysilicon layer, and then the floating gate from the first polysilicon layer using the second gate as a self-aligning mask. Metal coverage in the double layer of conductive lines is improved by rounding corners of glass and intermetal layers by means of glass reflow and planarization and wet/dry etching of the intermetal layer.

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