EPROM element employing self-aligning process

Details EPROM element employing self-aligning process EPROM element employing self-aligning process

1990-09-12

1992-02-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, H01L 21265, H01L 2170, H01L 2100

Patent

active

050913263

ABSTRACT:
A novel process is provided for fabricating contacts (46s, 40g, 46d) in a novel, completely self-aligned, planarized configuration for EPROM elements (66). The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.m and lower. The EPROM element comprises source (18) and drain (20) regions separated by a gate region (22) and is characterized by the gate region comprising two separate gates, a floating gate (40g) and a control gate (58), capacitively coupled together. The floating gate is formed on a gate oxide (38) over the substrate (16) and the gates are separated from each other and from the source and drain contacts by a dielectric (56). The EPROM element has two threshold voltages, one related to the operation of a "normal" MOS transistor and the other related to a "programmed" threshold, following programming of the transistor. Sensing the threshold voltage of the device permits a determination to be made whether the device is programmed. UV radiation erases the programming and restores the threshold voltage of the device to its pre-programmed level.

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patent: 4803176 (1989-02-01), Bower

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