Static information storage and retrieval – Floating gate – Particular biasing
Patent
1987-09-28
1989-07-25
Moffitt, James W.
Static information storage and retrieval
Floating gate
Particular biasing
G11C 1140
Patent
active
048520624
ABSTRACT:
An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.
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A. T. Wu, et al., "A Source-Side Injection Erasable Programmable Read-Only-Memory Device (SI-EPROM)," IEEE Electron Device Letters, vol. ED-7, No. 9, Sep. 1986, pp. 540-542.
Baker Frank K.
Hart Charles F.
Pfiester James R.
Fisher John A.
Moffitt James W.
Motorola Inc.
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