Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-05-21
2001-03-27
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185140, C257S319000, C257S320000
Reexamination Certificate
active
06208557
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to EPROM and flash memory cells and, more particularly, EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming.
2. Description of the Related Art
An electrically-programmable read-only-memory (EPROM) cell and a flash memory cell are non-volatile memories that retain data stored in the cell after power to the cell has been removed. EPROM and flash memory cells principally differ from each other in that EPROM cells are erased with ultraviolet (UV) light, while flash cells are electrically erased.
FIG. 1
shows a cross-sectional view that illustrates a prior-art EPROM or flash memory cell
100
. As shown in
FIG. 1
, cell
100
includes spaced-apart n+ source and drain regions
112
and
114
which are formed in a p-type substrate
110
, and a channel region
116
which is defined in substrate
110
between source and drain regions
112
and
114
.
In addition, cell
100
also includes a layer of gate oxide
120
which is formed over channel region
116
, and a floating gate
122
which is formed over gate oxide layer
120
. Further, cell
100
additionally includes a layer of interpoly dielectric
124
which is formed over floating gate
122
, and a control gate
126
which is formed over dielectric layer
124
.
Cell
100
is programmed by applying a programming voltage to control gate
126
, a drain voltage to drain region
114
, and ground to source region
112
. The programming voltage applied to control gate
126
induces a positive potential on floating gate
122
which, in turn, attracts electrons to the surface of channel region
116
to form a channel
130
.
In addition, the drain-to-source voltage sets up an electric field which causes electrons to flow from source region
112
to drain region
114
via channel
130
. As the electrons flow to drain region
114
, the electric field, which has a maximum near drain region
114
, accelerates these electrons into having ionizing collisions that form channel hot electrons near drain region
114
.
A small percentage of the channel hot electrons are then injected onto floating gate
122
via gate oxide layer
120
. Cell
100
is programmed when the number of electrons injected onto floating gate
122
is sufficient to prevent channel
130
from being formed when a read voltage is subsequently applied to control gate
126
.
Since electrons are injected onto floating gate
122
near drain region
114
, cell
100
is referred to as having drain-side injection. However, by altering the structure of the cell, electron injection can alternately take place near the source region.
When electrons are injected onto a floating gate near the source region, the cell is referred to as having source-side injection. U.S. Pat. No. 5,212,541 to Bergemont discloses a prior-art EPROM cell with source-side injection.
FIG. 2
shows a cross-sectional view that illustrates a source-side injection EPROM cell
200
as disclosed by the '541 patent.
FIG. 2
is similar to
FIG. 1 and
, as a result, utilizes the same reference numerals to designate the structures which are common to both cells.
As shown in
FIG. 2
, cell
200
differs from cell
100
in that source region
112
no longer lies directly below floating gate
122
and control gate
126
, but instead is spaced apart from the region that lies directly below floating and control gates
122
and
126
.
Further, cell
200
includes a polysilicon (poly) spacer
210
that is formed over source region
112
and a portion of channel region
116
, and is isolated from source region
112
, the portion of channel region
116
, floating gate
122
, and control gate
126
.
In operation, cell
200
is programmed in the same manner that cell
100
is programmed except that cell
200
also applies a low positive voltage to poly spacer
210
. Under these biasing conditions, the structure of cell
200
alters the drain-to-source electric field so that the electric field has a peak in the channel region that lies below the isolation region that separates poly spacer
210
from floating and control gates
122
and
126
.
As a result, channel hot electrons are formed in this channel region where a number of these hot electrons are injected onto floating gate
122
. As with cell
100
, cell
200
is programmed when the number of electrons injected onto floating gate
122
is sufficient to prevent channel
130
from being formed when a read voltage is subsequently applied to control gate
126
.
SUMMARY OF THE INVENTION
The present invention provides an electrically-programmable read-only-memory (EPROM) or a flash memory cell with source-side injection and a gate dielectric that traps hot electrons during programming.
The memory cell of the present invention, which is formed in a semiconductor material of a first conductivity type, includes spaced-apart source and drain regions of a second conductivity type which are formed in the material, and a channel region which is defined in the material between the source and drain regions. The channel region, in turn, has a first region, a second region, and a third region.
The cell also includes an isolation layer which is formed on the semiconductor material over the channel region. The isolation layer, in turn, includes a material, such as nitride, that has substantially more electron traps than hole traps so that the isolation layer is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.
The cell of the present invention also includes a first gate which is formed on the isolation layer over the first channel region, an isolation region which is formed on the isolation layer over the second channel region, and a second gate which is formed on the isolation layer over the third channel region.
The cell of the present invention is programmed by applying a programming voltage to the first gate, an intermediate voltage to the drain region, and a low positive voltage to the second gate. In addition, ground is applied to the source region and the semiconductor material.
The cell of the present invention is erased by applying a first erase voltage to the first gate, a second erase voltage to the drain region, and the first erase voltage to the second gate. In addition, ground is applied to the source region and the semiconductor material.
The cell of the present invention is read by applying a first read voltage to the first and second gates, and a second read voltage to the drain region. In addition, ground is applied to the source region and the semiconductor material.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized.
REFERENCES:
patent: 5168465 (1992-12-01), Harari
patent: 5284784 (1994-02-01), Manley
patent: 5338952 (1994-08-01), Yamauchi
patent: 5394360 (1995-02-01), Fukumoto
patent: 5402371 (1995-03-01), Ono
patent: 5422504 (1995-06-01), Chang et al.
patent: 5455792 (1995-10-01), Yi
patent: 5768192 (1998-06-01), Eitan
patent: 6011725 (2000-01-01), Eitan
Silicon Processing For The VLSI Era, vol. 2, Process Integration, Stanley Wolf Ph.D., Lattice Press, Sunset Beach, California, pp. 628-629.
Bergemont Albert
Kalnitsky Alexander
Limbach & Limbach L.L.P.
Mai Son
National Semiconductor Corporation
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