Metal treatment – Process of modifying or maintaining internal physical... – Chemical-heat removing or burning of metal
Patent
1985-07-02
1987-01-13
Saba, William G.
Metal treatment
Process of modifying or maintaining internal physical...
Chemical-heat removing or burning of metal
29571, 29576E, 29576W, 29577C, 29578, 29580, 148DIG26, 148DIG50, 148DIG85, 156612, 156649, 156657, 156662, 357 48, H01L 21205, H01L 2176
Patent
active
046362690
ABSTRACT:
A process is disclosed for manufacturing electrically isolated semiconductor device structures. The process includes the steps of providing a semiconductor substrate and selectively etching one surface of that substrate to form etched regions and unetched regions. In a single epitaxial growth step three separate epitaxial layers are grown overlying both the etched and unetched regions. The epitaxial layers are then shaped back to form a substantially planar surface and to expose portions of the first epitaxial layer. The exposed portion of the first epitaxial layer, in combination with the substrate, is suitable for the fabrication of a back contact power transistor. The second epitaxial layer, which follows the contour of the etched surface, bends upwardly and intersects the planar surface to substantially surround portions of the third epitaxial layer and to electrically isolate those portions of the third epitaxial layer from the substrate and first epitaxial layer. The portions of the third epitaxial layer are thus suitable for the implementation of an integrated control circuit function.
REFERENCES:
patent: 3370995 (1968-02-01), Lowery et al.
patent: 3456169 (1969-07-01), Klein
patent: 3566220 (1971-02-01), Post
patent: 3575731 (1971-04-01), Hoshi et al.
patent: 3587166 (1971-06-01), Alexander et al.
patent: 3740276 (1973-06-01), Bean
patent: 3753803 (1973-08-01), Nomura et al.
patent: 3764409 (1973-10-01), Nomura et al.
patent: 3793712 (1974-02-01), Bean et al.
patent: 3853644 (1974-12-01), Taruo et al.
patent: 4056413 (1977-11-01), Yoshimura
patent: 4089021 (1978-05-01), Sato et al.
patent: 4346513 (1982-08-01), Nishizawa et al.
patent: 4566174 (1986-01-01), Yasuda et al.
Chao et al., "Heavy Doping Isolation for CMOS Integrated Circuits" IBM Tech. Disc. Bull., vol. 25, No. 7A, Dec. 82, pp. 3350-3352.
Doo, V. Y., "High Capacitance PN Junction Capacitors by Etch Refill Method" IBM Tech. Disc. Bull., vol. 9, No. 7, Dec. 1966, pp. 920-921.
Doo, V. Y., "Junction Isolation for Isolating Integrated Devices Formed by an Etch and Regrowth Technique" IBM Tech. Disc. Bull., vol. 8, No. 4, Sep. 1985, pp. 668-669.
Fisher John A.
Motorola Inc.
Saba William G.
Warren Raymond J.
LandOfFree
Epitaxially isolated semiconductor device process utilizing etch does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Epitaxially isolated semiconductor device process utilizing etch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Epitaxially isolated semiconductor device process utilizing etch will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2354223