Active solid-state devices (e.g. – transistors – solid-state diode – Semiconductor is an oxide of a metal or copper sulfide
Reexamination Certificate
2002-08-29
2003-11-04
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Semiconductor is an oxide of a metal or copper sulfide
C257S289000, C257S613000
Reexamination Certificate
active
06642539
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to thin film devices having a functional metal oxide layer, for example, a perovskite ferroelectric memory or high dielectric constant capacitor material. In particular, the invention relates to forming such thin film devices on silicon substrates.
BACKGROUND ART
Significant advancements have been accomplished in the past few years in the growth and processing of ferroelectric and high dielectric metal oxide thin films for a variety of microelectronic applications. Much of the work has focused on potential integration of these metal oxide films into volatile and non-volatile memories although other applications are also being explored. These efforts blossomed in the early 1980s primarily through pioneering efforts in the sol-gel processing, chemical vapor deposition (CVD), and sputter deposition of multi-component metal oxide thin films. These techniques facilitated the fabrication of sub-micron thin films of ferroelectric materials such as lead zirconate titanate (PZT) and other cationically substituted derivatives of PZT on silicon substrates. Applications other than memories include cuprate thin films for superconducting junctions and microwave devices and magnetic perovskites for magneto transport devices.
The prototypical structure for a high-density non-volatile memory cell that has evolved from these efforts is schematically illustrated in
FIG. 1
, but other structures are available. A large number of memory cells, one of which is illustrated, are formed in a silicon substrate
10
. Ion implantation is used to dope a source
12
and drain
14
into the substrate
10
. A pass gate transistor structure including a gate oxide
16
and metallization
18
is formed over the gate region between the source
12
and drain
14
to produce a MOS transistor. Electrical power or sensing circuitry is selectively connected to the source
12
by an unillustrated line and is gated by the signal applied to the gate structure through the metallization
18
. The transistor structure is then covered with a first-level dielectric layer
20
typically of SiO
2
or a related silicate glass. A contact hole is etched in the oxide dielectric layer
20
over the transistor drain. Polycrystalline silicon is filled into the contact hole to form a silicon plug
22
making electric contact with the transistor drain
14
.
The ferroelectric device, in this case, a ferroelectric memory capacitor, is formed over the polysilicon plug
22
. The vertically oriented capacitor is electrically contacted at its bottom through the polysilicon plug
22
and silicon drain
14
of the transistor structure and at its more exposed top by a second signal line. The dramatic difference in chemistries between the ferroelectric oxides and the underlying silicon necessitates the introduction of a diffusion barrier to eliminate any diffusion of oxygen from the metal oxide ferroelectric layer or other oxide layers to the components of the semiconductor transistor. Even the oxidation of the top of the silicon plug
22
would create a insulative electrical barrier of SiO
2
between the ferroelectric capacitor cell and the silicon transistor. The fact that the barrier must be a good electrical conductor and form an ohmic contact to silicon further complicates the selection of barrier materials.
For reasons to be discussed immediately below, a typical barrier consists of a layer
24
of titanium nitride (TiN) and a layer
26
of platinum immediately underlying a lower electrode layer
28
. These layers
24
,
26
,
28
are patterned to form a lower ferroelectric stack. A shaped diffusion barrier layer
30
, for example, of titanium oxide (TiO
2
) is deposited and patterned to have an aperture over the top of the lower ferroelectric stack. A ferroelectric layer
32
is then deposited, for example of PZT or its generalization of lead lanthanum niobate zirconate titanate (PLNZT), followed by an upper electrode layer
34
, and an upper platinum barrier layer
36
. The TiO
2
diffusion barrier layer
30
, the ferroelectric layer
32
, the upper electrode layer
36
, and the upper platinum barrier layer
34
are patterned to have larger area than that of the aperture over the lower ferroelectric stack. These depositions complete the ferroelectric stack.
An SiO
2
inter-level dielectric layer
38
is deposited and patterned to have a via hole overlying the upper platinum electrode layer
36
of the ferroelectric stack. A contact barrier layer
40
, for example of conductive TiN or TiW, is coated at the bottom of the via hole, and a metallization
42
, for example, of aluminum or tungsten, is filled into the remainder of the via hole, thereby providing an upper electrical contact to the ferroelectric stack.
Platinum is chosen for the barrier, particularly the lower barrier, primarily because of its refractory nature and resistance to oxidation, unlike, for example, the more commonly used conductor aluminum. Platinum barriers enable ferroelectric capacitors with very desirable basic properties, such as large values of remanent polarization AP, ferroelectric film resistivities of greater than 10
10
&OHgr;-cm, and sufficient retention characteristics.
Titanium nitride is another obvious choice for a barrier layer, especially since it is already widely used in the semiconductor industry as a diffusion barrier. Unfortunately, TiN oxidizes at about 500° C., which is much lower than the optimum process temperature for ferroelectric materials. To overcome the shortcoming of the TiN in terms of temperature, platinum and iridium (Ir) have been used as materials for protective layers. Another common approach is to dope TiN with Al to form (Ti, Al)N or to use silicides or other complex structures. The most common approaches being currently explored use a combination of at least two layers to create a composite barrier layer, such as that in FIG.
1
. Taking the PZT ferroelectric material as an example, one approach uses the combination of (Ti, Al)N/(Pt, Ir) as the composite barrier. The structure of
FIG. 1
uses a special case of this composite barrier.
However, the above structure presents continuing problems. Even though platinum is a refractory metal and does not oxidize, it is nonetheless fairly porous to oxygen. That is, it does not prevent oxygen from diffusing to the underlying silicon plug and oxidizing a resistive surface layer there. Furthermore, such devices have been observed to suffer fundamental reliability problems. For example, if the test capacitors are repeatedly cycled for more than 10
7
to 10
8
bipolar cycles, the amount of remanent polarization still available becomes progressively smaller, and eventually the non-volatile capacitor functionally fails.
The use of platinum or iridium in the barrier or other parts of the stack structure presents other technological and strategic problems. First, dry etching of Pt or Ir is still very difficult although there have been some recent breakthroughs. A dry etch process, such as reactive ion plasma etching, is considered to be essential for commercial memories to be manufacturable with high yield. Since both Pt and Ir are relatively inert (although Ir does form stable oxides), the ability to form volatile reaction species during dry etching appears to be severely limited. Secondly, both Pt and Ir are considered to be precious metals, not only expensive but also of uncertain supply in such quantities required for widespread commercialization. As a result, the economics of supply and demand may impact the feasibility and dependability of using these precious metals in large quantities.
In view of the problems with platinum and iridium, one of the present inventors, Ramesh, and others have developed the use of other alloys and compounds that eliminate the need for including these precious metals. The results have been scientifically interesting and offer much promise. Dhote et al. in U.S. Pat. No. 5,777,356 describe the use of intermetallic alloys as the conducting barrier layer, without the use of Pt or Ir. An intermetallic alloy
Ramesh Ramamoorthy
Schlom Darrell G.
Guenzer Charles S.
Ngo Ngan V.
University of Maryland
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