Epitaxial silicon wafer with intrinsic gettering and a...

Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth from liquid or supercritical state – Having pulling during growth

Reexamination Certificate

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C117S089000, C117S935000, C428S450000, C428S310500

Reexamination Certificate

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06958092

ABSTRACT:
A wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer. In addition, the front surface of the wafer has an epitaxial layer, having a thickness of less than about 2.0 çm, deposited thereon. A process comprises heating a surface of a wafer starting material to remove a silicon oxide layer from the surface and depositing an epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant, and the wafer is cooled at a rate of at least about 10C./sec.

REFERENCES:
patent: 4314595 (1982-02-01), Yamamoto et al.
patent: 4376657 (1983-03-01), Nagasawa et al.
patent: 4437922 (1984-03-01), Bischoff et al.
patent: 4505759 (1985-03-01), O'Mara
patent: 4548654 (1985-10-01), Tobin
patent: 4851358 (1989-07-01), Huber
patent: 4868133 (1989-09-01), Huber
patent: 5327007 (1994-07-01), Imura et al.
patent: 5401669 (1995-03-01), Falster et al.
patent: 5403406 (1995-04-01), Falster et al.
patent: 5445975 (1995-08-01), Gardner et al.
patent: 5478408 (1995-12-01), Mitani et al.
patent: 5487358 (1996-01-01), Ohta et al.
patent: 5502010 (1996-03-01), Nadahara et al.
patent: 5502331 (1996-03-01), Inoue et al.
patent: 5525549 (1996-06-01), Fukada et al.
patent: 5534294 (1996-07-01), Kubota et al.
patent: 5539245 (1996-07-01), Imura et al.
patent: 5561316 (1996-10-01), Fellner
patent: 5587019 (1996-12-01), Fujie
patent: 5593494 (1997-01-01), Falster
patent: 5611855 (1997-03-01), Wijaranakula
patent: 5674756 (1997-10-01), Satoh et al.
patent: 5738942 (1998-04-01), Kubota et al.
patent: 5788763 (1998-08-01), Hayashi et al.
patent: 5820685 (1998-10-01), Kurihara et al.
patent: 5939770 (1999-08-01), Kageyama
patent: 5944889 (1999-08-01), Park et al.
patent: 6129787 (2000-10-01), Adachi et al.
patent: 6284384 (2001-09-01), Wilson et al.
patent: 6537655 (2003-03-01), Wilson et al.
patent: 43 23 964 (1994-01-01), None
patent: 0 503 816 (1992-09-01), None
patent: 0 536 958 (1993-04-01), None
patent: 0 716 168 (1996-06-01), None
patent: 3-9078 (1991-02-01), None
patent: 4-10544 (1992-01-01), None
patent: 5-155700 (1993-06-01), None
patent: 7-201874 (1995-08-01), None
patent: 7-321120 (1995-12-01), None
patent: 7-335657 (1995-12-01), None
patent: 8-045944 (1996-02-01), None
patent: 8-045945 (1996-02-01), None
patent: 8-045947 (1996-02-01), None
patent: 8-24796 (1997-07-01), None
patent: 11-067781 (1999-03-01), None
patent: 11-150119 (1999-06-01), None
patent: WO 98/38675 (1992-09-01), None
patent: WO 98/45507 (1998-10-01), None
Shimizu et al., “Excellence of Gate Oxide Integrity in metal Oxide semiconductor large scale integrated cicuits based on p/p thin film epitaxial silicon wafers”, Jap. Jour. Applied Physics vol. 36 (1997) pp. 2565-2570.
Abe et al, “Defect free surfaces of bulk wafers by combination of RTA and crystal growth conditions”.
T. Abe, “Innovated Silicon Crystal Growth And Wafering Technologies”, Electrochemical Soc. Proc., vol. 97, No. 3, 1997, pp. 123-133.
T. Abe, “Defect-Free Surfaces Of Bulk Wafers By Combination OF RTA And Crystal Growth Conditions”, (publication information unknown).
Falster, R., et al., “The Engineering of Silicon Wafer Material Properties Through Vacancy Concentration Profile Control and the Achievement of Ideal Oxygen Precipitation Behavior”, Mat. Res. Soc. Symp. Proc., vol. 510, 1998, pp. 27-35.
Hawkins, et al., “Effect of Rapid Thermal Processing on Oxygen Precipitation in Silicon”, Mat. Res. Soc. Symp. Proc., vol. 104, 1988, pp. 197-200.
Hawkins, et al., “The Effect of Rapid Thermal Annealing on the Precipitation of Oxygen in Silicon”, J. Appl. Phys., vol. 65, No. 9, 1989, pp. 3644-3654.
Herng-Der Chiou, “The Effects of Preheatings on Axial Oxygen Precipitation Uniformity in Czochralski Silicon Crystals”, J. Electrochem. Soc., vol. 139, No. 6, Jun., 1992.
Hirofumi et al., “Excellence of Gate Oxide Integrity in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits Based on P-/P-Thin-Film Epitaxial Silicon Wafers”, Jpn. J. Appl. Phys., vol. 36, 1997, pp. 2565-2570.
A. Hara et al., “Enhancement Of Oxygen Precipitation in Quenched Czochralski Silicon Crystals”, Journal of Applied Phys., vol. 66, No. 8, 1989, pp. 3958-3960.
Jacob, M., et al., “Influence of RTP on Vacancy Concentrations”, Mat. Res. Soc. Symp. Proc., vol. 490, 1998, pp. 129-134.
Kern, W., “The Evolution of Silicon Wafer Cleaning Technology”, J. Electrochem. Soc., vol. 137, No. 6, 1990, pp. 1887-1892.
Nadahara, et al., “Hydrogen Annealed Silicon Wafer”, Solid State Phenomena, vols. 57-58, 1997, pp. 19-26.
Pagani, M., et al., “Spatial variations in oxygen precipitation in silicon after high temperature rapid thermal annealing”, Appl. Phys. Lett., vol. 70, No. 12, 1998, pp. 1572-1574.
Schmolke et al., “Defect Depth Profile in Si(100) p/p Epitaxial Wafers”, The Electrochem Soc. Proc., vol. 98, No. 1, 1998, pp. 855-866.
Shimizu, Hirofumi et al., “Effects Of Surface Defects (COPs) On Isolation Leakage And Gate Oxide Integrity In MOS Large-Scale-Integrated-Circuit Devices And Cost Effective p-/p- Epitaxial Wafers”, Electrochemical Society Proceedings, vol. 99-1, pp. 315-323 (from a presentation on or about May 3, 1999).
F. Shimura, “Semiconductor Silicon Crystal Technology”, Academic Press, Inc., San Diego, CA, 1989, pp. 361-377.
R. Winkler et al., “Improvement Of The Gate Oxide Integrity By Modifying Crystal Pulling And Its Impact On Device Failures”, J. Electrochem. Soc., vol. 141, No. 5, 1994, pp. 1398-1401.
H. Zimmerman et al., “Vacancy Concentration Wafer Mapping In Silicon”, J. Crystal Growth, vol. 129, 1993, pp. 582-592.

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