Chemistry of inorganic compounds – Silicon or compound thereof – Oxygen containing
Reexamination Certificate
2000-09-21
2003-05-20
Hiteshew, Felisa (Department: 1772)
Chemistry of inorganic compounds
Silicon or compound thereof
Oxygen containing
C117S019000, C117S020000, C117S030000, C117S032000
Reexamination Certificate
active
06565822
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a large diameter epitaxial silicon wafer, a method for producing the same, and a substrate for an epitaxial silicon wafer.
BACKGROUND ART
Most of currently manufactured devices such as operational elements and memories are fabricated on a surface of a wafer, which is manufactured from a silicon single crystal that has been pulled by the Czochralski method (CZ method). In these devices, electric circuits are formed by utilizing an extremely thin surface layer of silicon wafer and operated. As means for improving quality of the surface layer and preventing latch-up, an epitaxial silicon wafer (hereafter also referred to as “epi-wafer”) is often used.
The epi-wafer is produced by growing an epitaxial layer (hereafter also referred to as “epi-layer”) on a wafer sliced from a silicon single crystal grown by the CZ method or the like. So far, as concerns epi-wafer, not so much attention has been paid for the quality of mirror surface silicon wafers used as substrates, since an epi-layer is deposited thereon.
In a crystal, there are generally two kinds of point defects formed during the crystal growth, i.e., one is vacancy and the other is self interstitial atom (interstitial-Si). A region where depressions, voids and so forth generated due to missing of silicon atoms are dominantly present among the above defects is called V-region. A region where dislocations generated due to presence of excessive silicon atoms and self interstitial atoms such as aggregations of excessive silicon atoms are dominant is called as I-region. In the V-region, there are grown-in defects considered to be originated from voids, i.e., aggregations of void-type point defects, such as FPD, LSTD and COP, at a high density. In the I-region, there are present L/D (abbreviation of interstitial dislocation loop: LSEPD, LFPD and so forth) defects, which are considered to be originated from dislocation loops, at a low density.
The boundary between the V-region and the I-region in the crystal is decided by the ratio of the crystal growth rate F [mm/min] and the temperature gradient G [° C./mm] along the crystal growth axis direction in the vicinity of the crystal growth interface, F/G (G is a value obtained by dividing the temperature difference of 12° C. between the melting point of silicon, 1412° C., and 1400° C. by a distance [mm] between the points of 1412° C. and 1400° C. along the axial direction). If this F/G exceeds a certain value, the crystal becomes the V-region, and if F/G is lower than the certain value, the crystal becomes the I-region.
Generally, the temperature gradient G along the crystal growth axis direction shows distribution along the radial direction in the crystal growth interface, and it becomes smaller at the center and becomes larger at the periphery of the crystal (see FIG.
1
). Since the crystal growth rate in a growing crystal is constant along the radial direction, distribution of F/G along the radial direction should be a reciprocal of the distribution of G along the radial direction. If F/G exceeds a certain value for the entire crystal growth interface, there is obtained a crystal that provides a wafer with no I-region for the entire plane. However, this may not usually be considered for a portion within 20 mm of the outermost periphery, since point defects can out-diffuse to the crystal surface and can be eliminated in this portion. For example, in case of a crystal having a usual resistivity (that having a resistivity of 0.03 &OHgr;·cm or more in the present invention), if F/G is 0.18 mm
2
/° C.·min or more for the entire inner portion except for the peripheral portion within 20 mm, there can be obtained a crystal providing the V-region for the entire plane. Conversely, if F/G is 0.18 mm
2
/° C.·min or less for the entire inner portion except for the peripheral portion within 20 mm, there can be obtained a crystal providing the I-region for the entire plane.
Under such a situation as described above, in the production of large diameter crystals having a diameter of 10 inches or more, which will be a main stream in future, the difference of G between the center and periphery of a crystal becomes large, and growth rate F is decreased due to increase in solidification latent heat. Therefore, it has become difficult to attain such an F/G that the V-region should be obtained for full radius of the crystal. For this reason, the I-region and the V-region tend to coexist in a wafer plane, and most of commercially available large diameter wafers contain the I-region.
By the way, P-type low resistivity wafers having a resistivity of 0.03 &OHgr;·cm or less, which are currently often used as substrates for epi-wafers, contain boron with a small covalent radius at a high concentration. Therefore, self interstitial atoms are likely to exist therein, and the value of F/G deciding the boundary of the I-region and the V-region becomes larger in connection with decrease in resistivity. Thus, most of commercially available P-type low resistivity wafers contain the I-region.
Under the recent stream of using a larger diameter of crystals and a lower temperature for the growth of epi-layers, it has become more frequent to produce epi-wafers comprising a large diameter crystal having a diameter of 10 inches or more, on which an epi-layer is grown at a lower temperature. Under such a circumstance, it has become more frequent to find, on the epi-wafers, particles that have not been observed on conventional wafers. Study of these particles has revealed that they correspond to particles that are detected on mirror wafer surfaces used as substrates by the high sensitivity particle measurement method, and they constitute projection type surface distortion observed as projections or particles when observed by AFM (atomic force microscope) or the like (they are also referred to as “projection-like particles” hereinafter).
It has been also revealed that these projections become still larger when an epitaxial layer is deposited, and they may also be detected as usual particles or the like. It has been also found that many of these projections are present in the I-region, which has conventionally been considered to have fewer defects. These projections and projection-like particles may cause breaking of wiring and so forth when an integrated circuit is formed on the wafer surface in the device production process. Therefore, they greatly affect device characteristics and reliability of devices, and thus their presence cannot be accepted in view of required quality of epi-wafers.
DISCLOSURE OF THE INVENTION
The present invention was accomplished in view of the problems described above, and its major object is to provide an epitaxial wafer of high quality with no projection-like particles on its epi-layer surface by forming a wafer not having the I-region for the entire surface from a single crystal of a large diameter and depositing an epitaxial layer thereon, and to produce a single crystal of a large diameter having no I-region for entire plane with good yield and high productivity, thereby improving productivity of epi-wafers and realizing cost reduction.
The present invention was accomplished in order to achieve the aforementioned object. According to the first aspect of the present invention, there is provided an epitaxial silicon wafer, which has no projections having a size of 100 nm or more and a height of 5 nm or more on an epitaxial layer. Such an epitaxial silicon wafer substantially does not have, on its epi-layer, projections or projection-like particles of the size defined above, which are harmful to quality of the wafer. Therefore, it scarcely suffer from breaking of wiring during the device production process, and thus there can be provided an epitaxial wafer of high quality, which does not adversely affect the device characteristics and the reliability of devices.
According to the second aspect of the present invention, there is provided a method for producing an epitaxial silicon wafer, wherein a silicon wafer which has
Fusegawa Izumi
Hoshi Ryoji
Ohta Tomohiko
Sakurada Masahiro
Sonokawa Susumu
Hiteshew Felisa
Oliff & Berridg,e PLC
Shin-Etsu Handotai & Co., Ltd.
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