Epitaxial contact fabrication process

Details Epitaxial contact fabrication process Epitaxial contact fabrication process

1982-08-18

1984-08-14

Rutledge, L. Dewayne

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29590, H01L 2122

Patent

active

044648243

ABSTRACT:
A process for fabricating an electrical contact which connects an epitaxial layer, well, or substrate with a metallic interconnect layer during the course of creating active integrated circuit devices in a semiconductor wafer. The process forms self-aligned contacts by establishing the contact locations coincident with the definition of the active regions, at an early step in the wafer fabrication process. Thereafter, a gate silicon dioxide layer and a polycrystalline silicon electrode layer are combined to mask the contact region surface from intermediate process environments, e.g., ion implantation and POCl.sub.3 diffusion operations. As the wafer fabrication process approaches conclusion, the contact region is opened by a selective etch of the polycrystalline silicon and the silicon dioxide layers, an enhancement implant into the surface of the contact region, a hydrogen environment annealing operation, and a deposition and patterning of the metallic interconnect layer.

REFERENCES:
patent: 4272881 (1981-06-01), Angle
patent: 4294002 (1981-10-01), Jambotkar et al.

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