Environment exchange control for material on a wafer surface

Coating processes – Centrifugal force utilized

Reexamination Certificate

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Details

C427S314000, C427S377000, C427S421100, C427S425000, C118S052000, C118S320000, C438S780000

Reexamination Certificate

active

06780461

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of microelectronic fabrication. More particularly, the invention relates to the fabrication of polymeric microelectronic structures, such as photoresist masks and low dielectric constant materials.
2. Discussion of the Related Art
The manufacturing of advanced semiconductors requires the production of circuit features at the sub micron level. A very sensitive photoresist is needed to define these features. The problems encountered in obtaining the maximum performance out of these sensitive photoresists is known to those skilled in the art of photolithography.
A class of new generation deep ultra-violet (DUV) chemically amplified photoresists based on “ACETAL” chemistry is required to produce features between 0.10-0.25 um using an exposure wavelength of 248 nm. One problem with ACETAL-based photoresists is that they are very sensitive to the chemical environment throughout the lithography process sequence. This is due to the fact that the chemical “deprotection” reaction that takes place during the post exposure bake (PEB) process requires the presence of moisture along with a photacid created during the previous exposure step. If the previous post application bake (PAB) process conditions and the stepper environment are not carefully optimized, and film moisture content decreases below a certain value, the ultimate lithographic performance of these photoresists will deteriorate significantly. Since deprotection has to occur at a precise time in the process sequence the moisture content at any given time of the process sequence is critical. What is needed is a solution to this moisture sensitivity.
The second problem with the ACETAL-based chemistries is that deblocking reaction rate of an ACETAL-based resist is much faster than the less sensitive DUV chemistries such as T-BOC resists due to a weak H—O physical bond. This is why the deblocking reaction starts at room temperature, thus causing contamination of the projection optics of the exposure tools (step and scanner) during the exposure step. What is also needed is a solution to this temperature sensitivity.
Heretofore, the requirements of obviating moisture and temperature sensitivity referred to above have not been fully met. What is needed is a solution that simultaneously addresses all of these requirements.
SUMMARY OF THE INVENTION
A primary goal of the invention is to improve the critical dimension (CD) tolerance of high performance DUV photoresist by controlling the environment in which the photoresist is thermally processed, before and/or after the exposure step. Another primary goal of the invention is to improve the mechanical and physical properties of materials (e.g. low dielectric constant, low-k liquid polymers) used in increasing the signal transmission speed of metal interconnects.
A first aspect of the invention is implemented in an embodiment that is based on a method for improving performance of a polymer, comprising: forming said polymer on a surface of a wafer; then locating said wafer in an environment so that said environment is adjacent to said polymer; and then controlling an exchange between said polymer and said environment. A second aspect of the invention is implemented in an embodiment that is based on an apparatus for controlling an exchange between an environment and a polymer on a surface of a wafer located in said environment, said apparatus comprising: a chamber adapted to hold said wafer, define said environment, and maintain said polymer in an adjacent relationship with said environment; and a heater coupled to said chamber. A third aspect of the invention is implemented in an embodiment that is based on a method for improving performance of a spin-on material, comprising: forming said spin-on polymer on a surface of a wafer; then locating said spin-on material in an environment so that said environment is adjacent to said spin-on material; and then controlling an exchange between said spin-on material and said environment.
These, and other, goals and aspects of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the invention without departing from the spirit thereof, and the invention includes all such modifications.


REFERENCES:
patent: 5358740 (1994-10-01), Bornside et al.
patent: 5658387 (1997-08-01), Reardon et al.
patent: 5670210 (1997-09-01), Mandal et al.
patent: 5766671 (1998-06-01), Matsui
patent: 5792590 (1998-08-01), Hirasawa
patent: 5814432 (1998-09-01), Kobayashi
patent: 5824604 (1998-10-01), Bar-Gadda
patent: 5885755 (1999-03-01), Nakagawa et al.
patent: 5954878 (1999-09-01), Mandal et al.
patent: 5968691 (1999-10-01), Yoshioka
patent: 6002108 (1999-12-01), Yoshioka
patent: 6027760 (2000-02-01), Gurer et al.
patent: 6040120 (2000-03-01), Matsushita et al.
patent: 6042994 (2000-03-01), Yang et al.
patent: 6254936 (2001-07-01), Gurer et al.
patent: 6468586 (2002-10-01), Gurer et al.
patent: 0 747 767 (1996-12-01), None
patent: 0 854 390 (1998-07-01), None
patent: 08-138993 (1996-05-01), None
Patent Abstracts of Japan, vol. 1998, No. 13, Nov. 30, 1998 (JP 10-214775, Aug. 11, 1988, Hideyuki).
Patent Abstracts of Japan, vol. 013, No. 138, Apr. 6, 1989, (JP 63-304250, Dec. 12, 1988, Mitsuro).
Patent Abstracts of Japan, vol. 014, No. 148, Mar. 20, 1990, (JP 02-008853, Jan. 12, 1990, Kazushi).
Patent Abstracts of Japan, vol. 1995, No. 09, Oct. 31, 1995, (JP 07-161619, Jun. 23, 1995, Keizo).
Patent Abstracts of Japan, vol. 008, No. 183, Aug. 23, 1984, (JP 59-074552, Apr. 27, 1984, Toshio).
Patent Abstracts of Japan, vol. 1998, No. 12, Oct. 31, 1998, (JP 10-198048, Jul. 31, 1998, Isao).

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