Entry point address circuit for microcode rom

Details Entry point address circuit for microcode rom Entry point address circuit for microcode rom

1985-12-06

1989-09-05

Shaw, Gareth D.

Static information storage and retrieval

Read only systems

G11C 700

Patent

active

048645354

ABSTRACT:
A multiplexer (76) for coupling selected instruction word bits to a microcode memory (22) as entry point addresses. The multiplexer (76) receives sixteen bits from an instruction word register (10) and, for normal word formats, couples the opcode (40) portion unchanged to the memory (22) as an entry point address. For special instruction word formats, various bits of the instruction word fields form an entry point address, while other bits are modified and coupled to memory (22) as column addresses to access selected memory sections.

REFERENCES:
patent: 3949370 (1976-04-01), Reyling, Jr. et al.
patent: 4032765 (1977-06-01), Epstein
patent: 4095278 (1978-06-01), Kihara
patent: 4300208 (1981-11-01), Jasmin et al.
patent: 4336602 (1982-06-01), Kruger
patent: 4370729 (1983-01-01), Bosch
patent: 4428047 (1984-01-01), Hayh et al.
patent: 4434465 (1984-02-01), McDonough et al.
patent: 4734885 (1988-03-01), Luich
patent: 4802126 (1989-01-01), Takayama

Affiliated with

Also associated with

Rating

Entry point address circuit for microcode rom does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Entry point address circuit for microcode rom, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Entry point address circuit for microcode rom will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-249422