Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-11-27
2004-11-02
Tang, Minh N. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C365S201000
Reexamination Certificate
active
06812726
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates generally to the field of semiconductor integrated circuits, and more particularly, to entering test mode and accessing of a packaged semiconductor device.
BACKGROUND
A semiconductor or integrated circuit (IC) device may comprise many miniaturized circuits implemented in a semiconductor substrate. IC devices must be tested in order to ensure proper operation before they are used. IC devices can be tested in a limited fashion using built-in self test (BIST) circuitry that is implemented within the IC devices themselves. BIST testing however, is incomplete and does not test all aspects of operation. Thorough testing of an IC device is accomplished with complex external testing equipment. In order for complex test equipment to be used, many dedicated input/output (I/O) pins are typically required for allowing the test equipment to input various test patterns, codes, and data, and to stress the circuitry of the IC device. In an environment where multiple IC devices are combined within a single package having a limited number of input/output leads, however, it can be difficult if not impossible to use external testing equipment for testing one or more of the devices thoroughly.
SUMMARY
According to one embodiment of the present invention, a system is provided for testing a first integrated circuit chip to be packaged along with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuit chips, and wherein the first integrated circuit chip is designed for normal operation and a test mode. The system includes a plurality of test buffer multiplexer circuits. Each test buffer multiplexer circuit is operable to receive a respective signal from the second integrated circuit chip when the first integrated circuit chip is in normal operation. Each test buffer multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit chip or an associated external terminal when the first integrated circuit chip is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit chip to transition between normal operation and the test mode.
According to another embodiment of the present invention, a memory chip is provided for packaging along with at least a system chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the memory chip and the system chip, and wherein the memory chip is designed for normal operation and a test mode. The memory chip includes a plurality of test buffer multiplexer circuits. Each test buffer multiplexer circuit is operable to receive a respective signal from the system chip when the memory chip is in normal operation, and is further operable to receive a respective signal from an associated external terminal when the memory chip is in test mode. A test input control buffer circuit is operable to receive a signal for causing the memory chip to transition between normal operation and the test mode.
According to yet another embodiment of the present invention, a method is provided for testing a first integrated circuit chip packaged along with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are shared by the first and second integrated circuit chips, and wherein the first integrated circuit chip is designed for normal operation and test mode. The method includes: transitioning the first integrated circuit chip from normal operation into the test mode; programming test codes in the first integrated circuit chip; and operating the first integrated circuit chip according to the programming codes and using test addresses and test patterns.
Important technical advantages of the present invention are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 4825414 (1989-04-01), Kawata
patent: 4873669 (1989-10-01), Furutani et al.
patent: 5326428 (1994-07-01), Farnworth et al.
patent: 5457400 (1995-10-01), Ahmad et al.
patent: 5479105 (1995-12-01), Kim et al.
patent: 5523697 (1996-06-01), Farnworth et al.
patent: 5535165 (1996-07-01), Davis et al.
patent: 5594694 (1997-01-01), Roohparvar et al.
patent: 5619461 (1997-04-01), Roohparvar
patent: 5657284 (1997-08-01), Beffa
patent: 5677885 (1997-10-01), Roohparvar
patent: 5751015 (1998-05-01), Corbett et al.
patent: 5751987 (1998-05-01), Mahant-Shetti et al.
patent: 5801452 (1998-09-01), Farnworth et al.
patent: 5805609 (1998-09-01), Mote, Jr.
patent: 5807762 (1998-09-01), Akram et al.
patent: 5825697 (1998-10-01), Gilliam et al.
patent: 5825782 (1998-10-01), Roohparvar
patent: 5923600 (1999-07-01), Momohara
patent: 5925142 (1999-07-01), Raad et al.
patent: 5936260 (1999-08-01), Corbett et al.
patent: 5959310 (1999-09-01), Akram et al.
patent: 5966388 (1999-10-01), Wright et al.
patent: 6026039 (2000-02-01), Kim et al.
patent: 6072326 (2000-06-01), Akram et al.
patent: 6087676 (2000-07-01), Akram et al.
patent: 6104658 (2000-08-01), Lu
patent: 6137167 (2000-10-01), Ahn et al.
patent: 6154860 (2000-11-01), Wright et al.
patent: 6157046 (2000-12-01), Corbett et al.
patent: 6188232 (2001-02-01), Akram et al.
patent: 6194738 (2001-02-01), Debenham et al.
patent: 6208157 (2001-03-01), Akram et al.
patent: 6216241 (2001-04-01), Fenstermaker et al.
patent: 6243839 (2001-06-01), Roohparvar
patent: 6243840 (2001-06-01), Raad et al.
patent: 6274937 (2001-08-01), Ahn et al.
patent: 6286115 (2001-09-01), Stubbs
patent: 6294839 (2001-09-01), Mess et al.
patent: 6298001 (2001-10-01), Lee et al.
patent: 6300782 (2001-10-01), Hembree et al.
patent: 6310484 (2001-10-01), Akram et al.
patent: 6320201 (2001-11-01), Corbett et al.
patent: RE37611 (2002-03-01), Roohparvar
patent: 6365421 (2002-04-01), Debenham et al.
patent: 6366487 (2002-04-01), Yeom
patent: 6392948 (2002-05-01), Lee
patent: 6395565 (2002-05-01), Akram et al.
patent: 6396291 (2002-05-01), Akram et al.
patent: 6407566 (2002-06-01), Brunelle et al.
patent: 6441479 (2002-08-01), Ahn et al.
patent: 6445625 (2002-09-01), Abedifard
patent: 6483760 (2002-11-01), Kang
patent: 6484279 (2002-11-01), Akram
patent: 6502215 (2002-12-01), Raad et al.
patent: 6507885 (2003-01-01), Lakhani et al.
patent: 6519171 (2003-02-01), Matsuzaki et al.
patent: 6519725 (2003-02-01), Huisman et al.
Inapac Technology, Inc.
Sidley Austin Brown & Wood LLP
Tang Minh N.
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