Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
2000-12-29
2004-05-18
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C713S320000, C713S323000, C713S324000, C713S330000, C713S340000, C710S305000
Reexamination Certificate
active
06738068
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains generally to computer systems. In particular, it pertains to managing transitions between power states in computer systems.
2. Description of the Related Art
As computer design has relied on more and more buses to accommodate increasing volumes of data transfers, many computers have incorporated a chip set, often referred to as the “core”, or “core controller”, to act as a centralized controller, providing separate interfaces and control logic to connect the processor (CPU), system memory, and various other peripheral devices. In particular, an increased focus on graphics has led to a separate graphics controller, interfaced to the core controller through a dedicated graphics bus. One version of the graphics controller interface is referred to as the Accelerated Graphics Port graphics controller (referred to herein as the AGP-GC), while its connecting bus is referred to as the AGP-GC bus. Read and write requests from the AGP-GC are used to initiate multi-byte memory transfers between the AGP-GC and memory that pass through the core controller.
FIG. 1
shows a conventional system
1
with an AGP-GC
13
, CPU
11
, system memory
14
, and peripheral bus controller
15
connected to core controller
10
. Peripheral bus controller
15
might actually be several different bus controllers, but is shown as a single consolidated bus controller for simplicity. Core controller
10
may include a graphics/memory control hub (GMCH)
18
to control transfers to/from memory
14
and AGP-GC
13
, and an I/O control hub (ICH)
19
to control transfers to/from peripheral bus controller(s)
15
.
AGP-GC
13
is connected to core controller
10
through bus
16
, which is shown as two separate sub-buses
16
A and
16
B. These sub-buses are shown separately because they act somewhat independently to perform different functions, even though they can be considered one bus. As shown in
FIG. 2
, sub-bus
16
A, sometimes referred to as the sideband command and address bus (SBA), carries requests from AGP-GC
13
to initiate block transfers to/from memory
14
. When such a request is received from AGP-GC
13
by GMCH
18
, the request is placed into queue
12
until it can be serviced. When the request is retrieved from the queue, GMCH
18
sets up and initiates the actual data transfer, which takes place over bi-directional sub-bus
16
B. Sub-bus
16
B can also carry commands from CPU
11
to AGP-GC
13
through GMCH
18
.
In a separate development, computer systems have incorporated low-power states to conserve energy, especially in battery-powered systems. Various portions of a computer system, such as the processor and core controller, can be placed in a low-power state when feasible, and reactivated when needed again. In particular, CPU
11
can be placed in various power states, commonly labeled C
0
(normal operation), C
1
(execute CPU halt instruction and wait for interrupt to restart CPU), C
2
(stop CPU clock, but allow other devices to communicate with memory by permitting memory snooping), and C
3
(sleep state—stop CPU clock, memory operations, and related bus operations). CPU
11
can be restarted (returned to C0) from states C2 or C3 by a signal from core controller
10
, which contains its power control logic in ICH
19
. Deeper sleep states (i.e., C4, C5, etc.) may also exist, but are not as well defined. For the purposes of this disclosure, they can be considered to be included with C3.
Entering low power state C3 can cause problems with the operation of AGP-GC
13
because entry into this state can prematurely terminate any AGP-GC transaction that is in progress, causing a loss of any untransferred data and loss or corruption of any requests remaining in queue
12
. Thus, from the time AGP-GC
13
places a request into queue
12
until the time the resulting data transfer has been completed, the system should avoid entering the C3 state. Unfortunately, a conventional AGP-GC interface bus
16
has no handshaking provision to allow AGP-GC
13
to notify GMCH
18
that AGP-GC
13
has a pending request for which the data transfer has not been completed.
A conventional method of minimizing these problems is to communicate the intention to enter a low power state to AGP-GC
13
a predetermined period of time before entering the sleep state by sending a Stop indication to the AGP-GC. This predetermined time period is supposed to be long enough so that AGP-GC
13
can stop issuing requests, and any requests that have already issued will have time to work their way through queue
12
and then complete their data transfers. Since the exact amount of time necessary to do these things is variable and somewhat unpredictable, a time period is chosen that is assumed to be sufficiently long to complete any data transfer that has been requested. A time period of 32 microseconds is typical. If less time is required to actually complete the transfer, the remaining time is wasted, which can affect the efficiency of the system and lead to increased power usage by unnecessarily delaying entry into a sleep state. However, if more than the allotted time is required to complete the transfer, some of the data will be lost when the time period expires and a low power state is entered before the data transfer completes. Thus, the problem of lost data and errors is reduced, but not eliminated, by the use of a predetermined delay between announcing an intent to enter the low power state and the actual entry into the low power state.
REFERENCES:
patent: 5471625 (1995-11-01), Mussemann et al.
patent: 5659715 (1997-08-01), Wu et al.
patent: 6052133 (2000-04-01), Kang
patent: 6292201 (2001-09-01), Chen et al.
patent: 6434688 (2002-08-01), Rhode et al.
Cline Leslie E.
Cohen Debra T.
Cooper Barnes
Jain Satchit
Nanduri Anil V.
Intel Corporation
Singh Dalip K
Travis John F.
LandOfFree
Entering and exiting power managed states without disrupting... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Entering and exiting power managed states without disrupting..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Entering and exiting power managed states without disrupting... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3191986