Enhancement-FET and depletion-FET with different gate length for

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357 2312, H01L 2980

Patent

active

051482444

ABSTRACT:
This invention provides an E/D integrated circuit obtained by connecting an enhancement transistor serving as a switching transistor to a depletion transistor serving as a load and having a gate length larger than a gate length of the enhancement transistor in series with each other.

REFERENCES:
patent: 4701646 (1987-10-01), Richardson
patent: 4814835 (1989-03-01), Tung
patent: 4963948 (1990-10-01), Awano
patent: 5021857 (1991-06-01), Suehiro

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