Enhancement-depletion CMOS circuit with fixed output

Details Enhancement-depletion CMOS circuit with fixed output Enhancement-depletion CMOS circuit with fixed output

1987-01-15

1988-04-26

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307451, 357 42, 357 91, 365 95, 365156, H01L 2986, H03K 19094, G11C 1700

Patent

active

047407140

ABSTRACT:
In a CMOS FET IC element including at least one pair of transistors with connected drains, one an N-channel MOSFET and one a P-channel MOSFET, the N-channel MOSFET having a first threshold voltage controlled by the implantation of an ion, and the P-channel MOSFET having a second threshold voltage control are implanted with the same type of ion, so that one of the pair of transistors, either the N-channel MOSFET or the P-channel MOSFET is of a type that is normally ON, and the other MOSFET is of a type that is normally OFF with any gate voltage between the two voltages supplied to their sources.

REFERENCES:
patent: 3639813 (1972-02-01), Kamoshida et al.
patent: 3939642 (1976-02-01), Morozumi
patent: 3958266 (1976-05-01), Athanas
patent: 4280272 (1981-07-01), Egawa et al.
patent: 4315781 (1982-02-01), Henderson
patent: 4461965 (1984-07-01), Chin
patent: 4496857 (1985-01-01), Chao
patent: 4594688 (1986-06-01), Uno

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