Enhancement and depletion mode selection layer for field effect

Details Enhancement and depletion mode selection layer for field effect Enhancement and depletion mode selection layer for field effect

1985-05-08

1986-10-07

Munson, Gene M.

357 15, H01L 2964, H01L 2980

Patent

active

046162429

ABSTRACT:
A field effect transistor structure suitable for use in an array of such structures disposed on a common substrate (14) is formed with a source terminal (22), a drain (24) terminal, and a gate terminal (26) upon an upper surface of a semiconductor chip. The chip includes a first layer (18) and a second layer (20), the first layer being grown epitaxially upon the second layer. The first layer forms a part of the gate terminal and the second layer includes a charge conduction channel coupling the source region and the drain region. A pocket layer (16) is disposed in the second layer beneath the terminals of the transistor structure and is doped with either an donor dopant or an acceptor dopant for altering the electric field at the conduction channel to insert electrons or remove electrons therefrom so as to convert an operating mode from either an enhancement mode to a depletion mode or from a depletion mode to an enchancement mode. A substrate with a terminal on the backside thereof may be placed contiguous the bottom of said second layer, the back terminal being applied to a negative source of voltage for a transistor structure of n-channel format. The semiconductor material of the chip is a obtained from compounds of elements of the groups III and V of the periodic table.

REFERENCES:
patent: 3767984 (1973-10-01), Shinoda et al.
patent: 4038563 (1977-07-01), Zuleeg et al.
patent: 4424525 (1984-01-01), Mimura

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