Enhanced word line driver to reduce gate capacitance for low vol

Details Enhanced word line driver to reduce gate capacitance for low vol Enhanced word line driver to reduce gate capacitance for low vol

1999-04-05

2000-08-15

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365102, 365104, G11C 800

Patent

active

061046655

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to word line drivers powered by a power supply with limited current driving ability, such as a charge pump, in integrated circuit memory devices; and specifically to memory devices including word line drivers powered with a boosted voltage during a read mode.
2. Description of the Related Art
Decreased power consumption and faster operating speeds are continuing trends in integrated circuit design. Lower voltages generally result in lower power operation. Standards are emerging that power integrated circuits at voltages lower than the typical 5 volts at present. For example, one low supply voltage which is emerging as a standard is specified to operate over a range of about 2.7 to 3.6 volts. Other, even lower supply potential standards are emerging. Low voltage supply ranges fall short of voltages needed for important applications. For example, in semiconductor memory devices, such as flash EEPROM or ROM, word lines may operate at a read potential of 4 volts or more. Voltage supply boosting circuitry is included on the integrated circuit to supply the required on chip voltages. Such boosting circuits have limited current driving capability, and thus limit the speed of devices.
The performance of boosting circuits is also limited by capacitance, which includes parasitic capacitance and the capacitance of drivers which rely on the boosted voltage. During a voltage boosting step, capacitance delays the voltage boost operation and increases the power required from the voltage boost circuits. Some major sources of capacitance are well capacitance, interconnect capacitance, oxide capacitance, and junction capacitance. Accordingly, it is desirable to provide a circuit for use with integrated circuits that decreases capacitance generally, and particularly decreases the capacitive load on the boosted voltage source during voltage boost operations.


SUMMARY OF THE INVENTION

An enhanced word line driver is disclosed that reduces capacitance for voltage boosting applications. Capacitance for low voltage applications is reduced by a load reduction circuit in the enhanced word line driver, implemented in an integrated circuit that includes a memory array. The load reduction circuit reduces the capacitive load placed by deselected word line drivers on the voltage boost source, particularly when the magnitude of the output of the voltage boost source increases.
The word line driver circuit includes a voltage source, a driver circuit, a feedback circuit, and a load reduction circuit. The voltage source supplies a first voltage. The driver circuit has an input, a two power inputs, and an output. The output is coupled to a word line. The first power input is coupled to the voltage source. In a selected mode, the word line driver circuit couples the word line to the first power input. In a deselected mode, the word line driver circuit couples the word line to the second power input. The feedback circuit has an input, an output, and a power input. The input of the feedback circuit is coupled to the output of the driver circuit. The power input of the feedback circuit is coupled to the voltage source. The load reduction circuit has an input, an output, and a control input. The input of the load reduction circuit is coupled to the output of the feedback circuit. The output of the load reduction circuit is coupled to the input of the driver circuit. In the deselected mode, the load reduction circuit reduces a capacitive load of the driver circuit on the voltage source.
In a second embodiment of the invention, an integrated circuit memory device includes a memory array, a plurality of address inputs, a voltage source, a decoder, and a plurality of word line driver circuits coupled to the voltage source, many of which are deselected, and one or a few of which are selected in a given access to the array. The memory array has a plurality of word lines coupled to memory cells in the array. The plurality of address inputs is adapted to receive addres

REFERENCES:
patent: 5263001 (1993-11-01), Youn et al.
patent: 5668758 (1997-09-01), Yiu et al.
patent: 5751643 (1998-05-01), Lines
patent: 5966331 (1999-10-01), Shiau et al.

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