Enhanced universal asynchronous receiver-transmitter

Details Enhanced universal asynchronous receiver-transmitter Enhanced universal asynchronous receiver-transmitter

1989-11-27

1990-08-14

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 24, 375 7, H04J 1500, H04L 514

Patent

active

049493337

ABSTRACT:
A universal asynchronous receiver-transmitter (UART) (54) is dislosed which is compatible with an industry standard yet provides additional features. The UART can be selectably operated in a synchronous or an asynchronous mode. First-in, first-out (FIFO) registers (404,424) are provided for both the receiver and transmitter portions of the UART, and a parity error and special character recognizer unit (412) on the receive side flags characters when they are placed in the reveive FIFO. Reception of a special character or one with a parity error is reported to the user via an interrupt mechanism (430). A random access memory (RAM) (413) with the special character recognized stores user-supplied patterns which are recognized as special characters. User-accessible status and control registers (408) have bit positions which enable and control the enhanced functions of the UART while maintaining compatability with the industry standard.

REFERENCES:
patent: 4345325 (1982-08-01), Gandini et al.
patent: 4509164 (1985-04-01), Mouftah
"MC68681 Technical Summary", Motorola, 1983.
"Designer's Handbook of Integrated Circuits", McGraw-Hill, 1984, Arthur Williams, pp. 13-13-13-17.
"DC-319-AA Dlart", Digital Equipment, Inc., 1982.

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