Enhanced test system for an application-specific memory scheme

Details Enhanced test system for an application-specific memory scheme Enhanced test system for an application-specific memory scheme

1995-05-16

1997-08-12

Beausoliel, Jr., Robert W.

Excavating

39518316, 395431, 39549704, 371 211, 365201, G06F 1100

Patent

active

056574436

ABSTRACT:
An enhanced test system in a processor having a memory supporting multiple memory schemes. The memory is partitioned into memory blocks and memory sub-blocks. A plurality of uniform data units each comprising a plurality of data fields is written to and read from each successive memory block in a FIFO manner so that a data field within each data unit, having a maximum field width, occupies each of the multiple memory locations at least once during testing. The enhanced test system maximizes the number of adjacent full-width data fields to test vertically and horizontally for field overflow within memory by writing and reading seriatim by data unit or partitioned by data field width, in adjacent memory blocks and sub-blocks, or overlapping memory blocks and overlapping sub-blocks.

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patent: 5388104 (1995-02-01), Shirotori
patent: 5479413 (1995-12-01), Sicola

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