Enhanced signal integrity bus having transmission line segments

Wave transmission lines and networks – Plural channel systems

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333 33, 333 81A, H01P 300

Patent

active

058050302

ABSTRACT:
An arrangement in which resistors are interposed on a bus line to attenuate reflected spurious pulses. The resistors are positioned on the bus so as not to be between a processor and its cache memory, but so as to be between the combination of the processor and cache memory and components such as a peripheral controller and a memory controller. The resistors reflect a portion of the pulse energy and attenuate the pulse energy passing through them. In another aspect of the invention, the traces making up the bus are arranged so that the intertrace distance is greater than a distance between the traces and an internal reference plane. This causes magnetic energy radiated by an aggressor trace to encounter the reference plane before it encounters a victim trace. This also reduces the amount of magnetic cross-coupling.

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patent: 3134950 (1964-05-01), Cook
patent: 4813047 (1989-03-01), Toda
patent: 5027088 (1991-06-01), Shimizu et al.

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