Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent
1995-03-23
1996-09-24
Gaffin, Jeffrey A.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
361 91, 361111, 361118, H02H 904
Patent
active
055596592
ABSTRACT:
An integrated circuit ESD protection technique includes a protection circuit having a series resistor-capacitor circuit connected between power supply bondpads. The resistor-capacitor circuit provides a desired time constant for control of active drive circuitry that controls a protective transistor also connected between the bondpads. The time constant is chosen to be short enough to prevent conduction of the protective transistor during normal operation and power-up, while still allowing conduction of the protective transistor during the initial phase of an ESD event. A feedback resistor is connected in parallel with the active circuitry, thereby lengthening the time that the protective transistor conducts during an ESD event. In this manner, the ESD current is more completely conducted through the protective circuitry, so that the level of protection is increased.
REFERENCES:
patent: 4766334 (1988-08-01), Warner
patent: 5255146 (1993-10-01), Miller
Fox James H.
Gaffin Jeffrey A.
Jackson Stephen
Lucent Technologies - Inc.
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