Enhanced rake structure

Details Enhanced rake structure Enhanced rake structure

2004-03-04

2010-10-26

Fan, Chien M (Department: 2611)

Pulse or digital communications

Spread spectrum

Direct sequence

C375S130000

Reexamination Certificate

active

07822106

ABSTRACT:
A rake architecture for a frequency division duplex (FDD) and use also in TDD and TD-SCDMA type communications system, designed to significantly reduce the memory capacity required and thereby also reduce an area on the die of an application specific integrated circuit (ASIC) into which the memory is integrated. A single circular buffer, preferably of the shared memory type is shared by all of the rake fingers of a rake receiver to significantly reduce the hardware and software required to time align multipath signals received by a UE from a base station. This unique time alignment technique also reduces the number of code generators required to track a plurality (typically three) of base stations.

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Harju et al., “A Flexible Rake Receiver Architecture for WCDMA Mobile Terminals”, Third IEEE Signal Processing Workshop on Signal Processing Advances in Wireless Communications, Taoyuan, Taiwan, Mar. 2001, pp. 9-12.
Harju et al., “A Flexible Rake Receiver Architecture for WCDMA Mobile Terminals”, Third IEEE Signal Processing Workshop on Signal Processing Advances in Wireless Communications, Taoyuan, Taiwan, pp. 9-12, (Mar. 2001).
Harju et al., “A Flexible Rake Receiver Architecture for WCDMA Mobile Terminals”, Third IEEE Signal Processing Workshop on Signal Processing Advances in Wireless Communications, Taoyuan, Taiwan, pp. 9-12, (Mar. 2001).

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