Enhanced rake structure

Details Enhanced rake structure Enhanced rake structure

2001-12-27

2004-08-03

Liu, Shuwang (Department: 2634)

Pulse or digital communications

Spread spectrum

Direct sequence

C375S130000, C375S133000, C375S134000, C375S136000, C375S137000

Reexamination Certificate

active

06771693

ABSTRACT:

BACKGROUND
The present invention relates to a rake architecture employed in CDMA communication systems. More particularly the invention relates to a rake architecture employing a shared memory designed to significantly reduce the memory capacity required and thereby also reduce a die area of an application specific integrated circuit (ASIC) for the rake architecture without any reduction in system capabilities. The architecture may be employed in all types of communication systems employing a rake receiver including, but not limited to, frequency division duplex (FDD), time division duplex (TDD), and time division-synchronous code division multiple access (TD-SCDMA).
Rake receivers are utilized in many types of communications systems. In the wide band code division multiple access (W-CDMA) type of system, a base station transmits primary and secondary sync codes as well as a common pilot channel (CPICH), the pilot signal being unique to each base station. Wireless mobile units (UEs) then receive and synchronize to these codes in order to establish and support a communication.
In one example, a UE can track three or more base stations. A rake receiver is utilized to despread transmissions received from base stations through utilization of a cross correlator and a code generator, as is conventional. The UE receiver receives both direct (i.e., line of sight) RF waves as well as delayed (i.e. multipath) waves due to different transmission path lengths, reflections, etc. Since the direct wave is not necessarily the strongest signal or is not a strong enough signal for reception purposes, synthesizing (i.e. combining) the energy of the direct waves with the energy of delayed waves results in a better signal. Each finger of a rake receiver is provided with a cross-correlator and code-generator for performing despreading. Time offset is adjusted using a delay circuit whereupon all the signals are added together after imposing the appropriate delays to these signals.
The rake fingers work in conjunction with a cell search mechanism and the rake finger locator.
FIG. 1
shows the basic timing of a frame. One ten millisecond (10 m sec) synchronization channel (SCH) radio frame is divided into fifteen (15) slots labeled zero (0) through fourteen (14). Each base station transmits a primary sync code and a secondary sync code as well as a common pilot channel (CPICH). Unlike the primary and secondary sync codes that are present only during the first 256 chips of each slot, the CPICH is present during the entire frame and repeats every frame, in addition to being unique for each base station. The rake finger locator uses this uniqueness to perform a correlation against the CPICH from each of the possible base stations in the area of the UE. After the correlation is performed, the rake finger locator determines which peak to assign to which finger of the rake receiver. As was mentioned hereinabove, each UE is typically required to track up to three (3) or more base stations, which capability is due to handover requirements.
Referring to
FIG. 3
, a simplified block diagram of a conventional code tracker
10
is shown. Each rake finger is provided with a code tracker
10
. A code generator
12
is provided with a code for a specific base station. The code timing must be offset to compensate for the current time offset from the start of the frame for the assigned peak. An interpolator and decimator filter
14
produces early, late and punctual outputs at
14
a,
14
b
and
14
c
respectively. The early and late outputs are utilized to keep the punctual output centered in the chip time.
The early, late and punctual outputs are despread with the code for the specific base station at
16
,
18
and
20
respectively. The early and late despread signals undergo integration and dumping at integration and dumping devices
22
and
24
, squaring at squaring devices
26
and
28
and are summed at
30
to produce an error signal e(t).
The punctual output also undergoes integration and dumping at integration and dumping device
34
, the output of which passes through moving average filter
36
and hard limiter
38
for application to normalization circuit
32
, together with the error sum e(t) outputted from summing circuit
30
. The normalized output is then passed through a feedback path to the interpolator and decimator
14
through loop filter
40
, accumulator
42
, amplifier
44
, hard limiter
46
, delay estimate processor
48
and quantitizer
50
, to provide a delay estimate to the interpolator and decimator
14
, for purposes of keeping the punctual output centered in the chip time. If the error becomes too large for the code tracker to track, the code generator
12
will be adjusted. The interpolator and decimator filter
14
basically breaks the chip time into, for example, eight (8) segments. Based on the error signal, one of the eight (8) segments is selected. As time progresses and, if the error continues to increase, a different output is selected from the filter
14
. Eventually, if the error is great enough that chip time runs out, at this point the pilot generator
12
is adjusted. The pilot generator
12
is usually a linear feedback shift register (LFSR), that is clocked (i.e., advanced) at the chip rate. If the pilot generator needs to be advanced at the next chip time, it will actually advance twice for that chip time. Conversely, if the pilot generator needs to be delayed, the pilot generator will hold its current value for a second chip time.
FIG. 2
shows a typical multipath. Each of the higher value points represents a multipath.
Each of the punctual outputs is fed into separate time delay elements (not shown) of the rake receiver. The purposes of time delay elements is to remove the time ambiguity, shown in
FIG. 2
, from the various multipaths. All of the energy remaining after code tracking is then summed in a data estimator (not shown) and is despread and descrambled into symbols.
Referring to
FIG. 4
, a conventional rake structure comprising of six (6) rake fingers is shown. Since all of the rake fingers are substantially identical in design and function, only one is shown in detail in
FIG. 4
, for purposes of simplicity. As was set forth hereinabove, the code tracker
10
shown in
FIG. 3
, and also shown in simplified block diagram form in
FIG. 4
, produces a punctual output
14
c
(see
FIG. 3
) which is fed into a delay element
52
which is preferably a circular buffer having a read port and a write port. A memory write pointer
54
increments the memory contents at a chip rate to locations where a punctual input is written and continually points to the next chip location within buffer
52
. A read pointer
56
also increments at the chip rate, but is offset from the write pointer
54
based at the number of chips offset from the referenced slot timing. The fine offset is obtained from the code offset circuitry
56
which receives the chip offset at
56
a
, an output from the code tracker at
56
b
and the output from code generator
58
at
56
c
, providing a fine offset for further adjustments of the memory read pointer
56
. The buffer
52
provides a time aligned output. It should be understood that the remaining rake fingers “
2
” through “
6
” operate in a similar fashion.
SUMMARY
The main advantage of the present invention resides in providing an apparatus and method to share the (possibly) many small memories needed to align the tracked multipaths and to move the shared memories ahead of the code tracker. Although the alignment of the multipaths and tracking of their movement is still performed by the code tracker, the code tracker now receives its data from a shared buffer of input symbols versus the more conventional method of sending the input stream to all code trackers and requiring that each code tracker buffers the results and then provides the required delay to obtain alignment.
The invention utilizes a circular buffer, preferably in the form of a shared memory, and has a memory read pointer for each rake finger to provide an offset from the locati

Affiliated with

Also associated with

Rating

Enhanced rake structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Enhanced rake structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced rake structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3352555