Enhanced processor buffered interface for multiprocess systems

Details Enhanced processor buffered interface for multiprocess systems Enhanced processor buffered interface for multiprocess systems

1995-06-01

1997-05-27

Tung, Kee M.

395401, 395427, 395309, 395412, 395512, 395520, G06F 1200

Patent

active

056340346

ABSTRACT:
An Enhanced Processor Buffered Interface (22c) for use in a multiprocessor system (10). The Enhanced Processor Buffered Interface executes an Atomic Fetch and Add operation for maintaining multiprocessor consistency and for minimizing the required participation of an attached processor (22a) in reading and writing locked memory locations, supports interleaved memory banks (22d) that operate with burst mode memory accesses at rates of up to 400 MBytes/sec, includes switchable state machines (52, 54, 100) to selectively provide wait-states as required for supporting different memory access timings, and furthermore provides an improved serial interface to an external multi-element LED display (110).

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