Enhanced prescaler phase interface

Details Enhanced prescaler phase interface Enhanced prescaler phase interface

1999-02-25

2000-08-22

Wambach, Margaret R.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

H03K 2100

Patent

active

061083933

ABSTRACT:
A programmable prescaler for scaling an input frequency into a desired output frequency including an input divider having an input connected to the input frequency and a divided output, a first counter, having an input connected to the divided output of the input divider and a terminal count output; and a second counter coupled to the terminal count output of the first counter having a scaled-frequency output. The second counter may be a divide by two counter, and may be coupled to the terminal count output of the first counter via the input divider. The input divider further may further include a plurality of divider stages, the input frequency and the terminal count output being cascaded through the plurality of divider stages, and wherein the second counter is coupled to the terminal count output of the first counter via the plurality of divider stages of the input divider. The terminal count output of the first counter may be coupled to a first divider stage of the plurality of divider stages, and an output of the first divider stage of the plurality of divider stages may be connected to a clock input of the second counter. The first counter may be a programmable binary counter. The scaled frequency output may be a signal having a duty cycle of approximately 50% and a frequency of one-half the desired output frequency. Additionally, the programmable prescaler may further comprise an edge detector coupled to the scaled frequency output of the second counter.

REFERENCES:
patent: 4575867 (1986-03-01), Hogue
patent: 5878101 (1999-03-01), Aisaka
patent: 5940467 (1999-08-01), Fransson
patent: 5966421 (2000-02-01), Haubursin et al.
patent: 6031425 (2000-02-01), Hasegawa

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