Enhanced phase and frequency detector that improves...

Details Enhanced phase and frequency detector that improves... Enhanced phase and frequency detector that improves...

2006-12-26

2006-12-26

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S012000

Reexamination Certificate

active

07154304

ABSTRACT:
A system and method of reducing the pulse width differential in a phase frequency detector (PFD) is provided. In a first embodiment, a PFD is construed using a plurality of flip-flops (or clocking devices) and a plurality of logic gates. A first set of flip-flops are adapted to receive a plurality of inputs and a plurality of clocks and to latch the inputs at transitions in the clocks. A first logic gate is then used to reset the first set of flip-flops and a second set of flip-flops if the inputs are latched (i.e., the clocks are active). If an input is not latched (i.e., a clock is inactive), then the first and second set of flip-flops are not reset, and the outputs of the PFD are forced to zero. Once the inactive clock is reactivated, a third set of flip-flops is used to hold the first set of flip-flops in a reset state for a period of time (e.g., half a clock cycle). Once the period of time elapses, the first set of flip-flops is released from its reset state, and normal operation is resumed. In a second embodiment, a signal (or an alarm) is provided to indicate that a clock has become inactive. In a third embodiment, at least one logic gate is used to force the first set of flip-flops into a reset state. This can be done, for example, when changing a clock's source or switching clocks.

REFERENCES:
patent: 5936430 (1999-08-01), Patterson
patent: 6285219 (2001-09-01), Pauls
patent: 6590427 (2003-07-01), Murphy et al.
patent: 6617884 (2003-09-01), Wang et al.
patent: 6646478 (2003-11-01), Lamb
patent: 2001/0007436 (2001-07-01), Dosho et al.
patent: 2003/0090296 (2003-05-01), Yoo

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