Enhanced PFET using shear stress

Details Enhanced PFET using shear stress Enhanced PFET using shear stress

2007-09-25

2007-09-25

Louie, Wai-Sing (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257SE21548

Reexamination Certificate

active

10905589

ABSTRACT:
A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the portion, and trench isolation regions located immediately adjacent to the source and drain regions. At least portions of the trench isolation regions include stress materials such that the materials generate shear stresses in the channel region.

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