Enhanced parity detection for wide ROM/PROM memory structure

Details Enhanced parity detection for wide ROM/PROM memory structure Enhanced parity detection for wide ROM/PROM memory structure

1986-09-08

1989-02-28

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

048092797

ABSTRACT:
A wide ROM-PROM memory is structured of multiple memory chips in parallel plus an auxiliary parity memory chip to hold parity bits for each corresponding addressable location in each memory chip. Sensing means is provided to check parity of data bits read from each memory location to verify integrity of the read-out.

REFERENCES:
patent: 3789204 (1974-01-01), Barlow
patent: 3944800 (1976-03-01), Beck et al.
patent: 4016409 (1977-04-01), Kim
patent: 4019033 (1977-04-01), Parmet
patent: 4271521 (1981-06-01), Mahmood
patent: 4295219 (1981-10-01), Draper et al.
patent: 4355393 (1982-10-01), Kubo et al.
patent: 4453251 (1984-06-01), Osman
patent: 4464755 (1984-08-01), Stewart et al.
patent: 4612640 (1986-09-01), Mehrotca et al.
Sellers et al., Error Detecting Logic for Digital Computers, McGraw Hill, New York, 1968, pp. 207-211.

Affiliated with

Also associated with

Rating

Enhanced parity detection for wide ROM/PROM memory structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Enhanced parity detection for wide ROM/PROM memory structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced parity detection for wide ROM/PROM memory structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1374655