Enhanced parallelism in trace scheduling by using renaming

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

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Details

C717S154000, C717S140000, C717S128000

Reexamination Certificate

active

06948162

ABSTRACT:
A method includes scheduling instructions within a trace disregarding data dependencies from off trace basic blocks. After scheduling, errors caused by instruction movement are corrected. By disregarding data dependencies from off trace basic blocks, more parallelism is exposed resulting in more instruction motion. In this manner, efficiency is maximized.

REFERENCES:
patent: 5828886 (1998-10-01), Hayashi
patent: 5867711 (1999-02-01), Subramanian et al.
patent: 6076159 (2000-06-01), Fleck et al.
patent: 6449713 (2002-09-01), Emer et al.
patent: 6526572 (2003-02-01), Brauch et al.
patent: 6651164 (2003-11-01), Soltis et al.
patent: 2003/0079211 (2003-04-01), Lueh
P. Geoffrey Lowney et al.,The Multiflow Trace Scheduling Compiler, The Journal of Supercomputing, 7, 51-142 (1993).

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