Optics: measuring and testing – By alignment in lateral direction – With light detector
Reexamination Certificate
2000-06-20
2004-04-27
Lee, John R. (Department: 2881)
Optics: measuring and testing
By alignment in lateral direction
With light detector
C430S022000
Reexamination Certificate
active
06727989
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates to overlay control in semiconductor processing, and in particular, a method of providing enhanced overlay measurement marks for control in semiconductor processing to overcome the limitations of overlay measurements marks that give an overlay shift range comparable to the measurement tools uncertainty and gives only stepper or scanner mechanical alignment errors but fails to provide accurate image placement error information due to stepper or scanner exposure conditions.
2. Description of Prior Art
In general, an overlay measurement mechanism is utilized in measuring an overlay error between multi patterns on a semiconductor body of a particular pattern formed by photolithographic techniques. The photolithographic technique entails the exposure of the surface of a semiconductor body or chip to a particular pattern, and the subsequent formation or development of that pattern into a permanent form through the use of wet or dry etching techniques that create various regions and structures on the surface of the semiconductor body or chip.
It is known that photolithographic procedures require the employment of masks to define those portions of the semiconductor material where various elements of semiconductor devices are to be located. Different parts or elements of the semiconductor devices must be located at precisely defined distances from one another, and it is desirable that each of the mask used in forming the semiconductor devices be aligned with respect to one another as precisely as possible, both in vertical and horizontal directions.
One method of determining alignment as well as the extent of processing is done visually by an operation that examines the surface of the semiconductor wafer and the mask under a microscope. The use of marks on the masks and on the wafer facilitates the monitor or measurement of misalignment. In any event, visual measurement procedures are very time consuming and subject to human errors. Further, a large number of measurements across the wafer from wafer to wafer are very difficult and in large scale production processes it is desirable to obtain a statistical base of information on the quantity and relative alignment of elements across the wafer from a large number of processed wafers.
U.S. Pat. No. 4,571,538 disclose a method for affecting mass alignment measurement structure during semiconductor fabrication by quantitatively measuring the relative alignment of elements on a surface of a semiconductor formed by two sequential masking steps during processing, wherein a fixed pattern of rectangular images are formed on a first mask, and a fixed pattern of repeating U-shaped images are formed on a second mask. The semiconductor material is processed so that the rectangular images on the first mask align with the U-shaped images on the second mask, whereupon an electrical probe is applied to opposed ends of the boustrophederal pattern formed and the electrical resistance measured to determine a parameter related to relative alignment of elements on the semiconductor.
A method of producing a semiconductor device utilizing an alignment correcting method is disclosed in U.S. Pat. No. 5,989,762, wherein a designated number of wafers are selected out of a single lot to have their alignment marks measured in terms of coordinates. Thereafter, a preselected number of wafers are selected out of the wafers having undergone measurement in the descending order with respect to closeness to a mean value or a center value of scattering, exposed and then developed. An alignment correction value is calculated on the basis of developed wafers.
U.S. Pat. No. 5,438,413 disclose a process for measuring overlay misregistration during semiconductor wafer fabrication. The method of inspecting the semiconductor wafer utilizes precision optical inspection methods and apparatus and performs microscopic measurement of alignment between at least two process layers on integrated circuit wafers using a coherence probe microscope in combination with electronic image processing. Data obtained from different planes is then used to calculate the magnitude and phase of the mutual coherence between an object wave and a reference wave for each pixel in the image planes, and synthetic images are formed, the brightness of which is proportional to either the complex magnitude or the phase of the mutual coherence as the optical path length is varied. The difference between synthetic images relating to target attribute position and bullet attribute position is then used as a means for detecting misregistration between the processing layer including the bullet attribute and the processing layer including the target attribute.
A method for measuring an overlay error between multiple patterns in a semiconductor device is disclosed in U.S. Pat. No. 5,48,500. The process entails forming a first overlay measurement pattern on a first selected portion of a scribe line by a first mask formed considering the margin between the first mask pattern and a second mask pattern, with the first overlay measurement pattern consisting of two patterns spacing parallel to each other. A second overlay measurement pattern is formed on a second selected portion of the scribe line by a second mask which is formed considering the margin between the second mask pattern and a third mask pattern so as not to superimpose the first overlay measurement pattern, with a second overlay measurement patterns consisting of two patterns spacing parallel to each other. Thereafter, a third overlay measurement pattern is formed on the scribe line by a third mask which is used to form the third mask pattern, with the third overlay measurement pattern forming at the center of the inside of the first and second overlay measurement patterns. The distance between the first overlay measurement patterns and the third overlay measurement patterns, and the distance between the second overlay measurement patterns and the third overlay measurement patterns are then measured to ascertain the error between the multi patterns in the semiconductor device.
A phase shifting overlay mark that measures exposure energy and focus during an alignment process forming a pattern of a semiconductor device is disclosed in U.S. Pat. No. 5,770,338. The overlay mark includes an inner box and an outer box to concurrently measure exposure energy and focus, wherein the changes of the exposure energy and the focus are represented by a phase shift between the inner and outer boxes in the X-axis and Y-axis.
There is a need in the art of measuring overlay misregistration or overlay alignment to: extend the overlay measurement range; increase the accuracy of overlay measurement results; and provide results in controlling stepper overlay alignment as well as scanner exposure conditions.
SUMMARY OF THE INVENTION
One object of the present invention is to extend the overlay measurement range during manufacturing or fabrication of semiconductor devices.
A further object of the present invention is to increase the accuracy of overlay measurement results during fabrication of semiconductor devices.
A further object of the present invention is to provide results for controlling stepper overlay alignment as well as stepper exposure conditions during manufacturing of semiconductor devices.
In general, the invention overlay measurement mark and method of measuring an overlay error between multiple patterns in a semiconductor device that overcomes the uncertainty of overlay shift range that is comparable to the measurement tools, and the limitation that gives only stepper or scanner mechanical alignment error and does not provide accurate image placement error information due to stepper or scanner exposure conditions is accomplished by providing overlay measurement marks in which a pair of resist/arc stacks are printed on a prior level located at a different focus level from the conventional level overlay measurement marks, and additionally, providing different feature marks placed along the conventional
Gould Christopher
Kunkel Gerhard
Yin Xiaoming
Kalivoda Christopher M.
Lee John R.
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